From: Jan Kiszka <jan.kiszka@siemens.com>
To: Uladzimir Bely <ubely@ilbers.de>, <isar-users@googlegroups.com>
Subject: Re: [PATCH 2/2] opensbi-sifive-fu540: Fix build with binutils 2.38
Date: Thu, 1 Sep 2022 13:21:11 +0200 [thread overview]
Message-ID: <0ff9a2e3-5aec-f604-d1d4-6978193403c6@siemens.com> (raw)
In-Reply-To: <20220901045201.9294-3-ubely@ilbers.de>
On 01.09.22 06:52, Uladzimir Bely wrote:
> Backport of https://github.com/riscv-software-src/opensbi/commit/5d53b55
> from opensbi-1.1.
>
> Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
> ---
> ...akefile-fix-build-with-binutils-2.38.patch | 58 +++++++++++++++++++
> .../opensbi/opensbi-sifive-fu540_0.9.bb | 1 +
> 2 files changed, 59 insertions(+)
> create mode 100644 meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
>
> diff --git a/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch b/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
> new file mode 100644
> index 00000000..d52a4695
> --- /dev/null
> +++ b/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
> @@ -0,0 +1,58 @@
> +From 5d53b55aa77ffeefd4012445dfa6ad3535e1ff2c Mon Sep 17 00:00:00 2001
> +From: Aurelien Jarno <aurelien@aurel32.net>
> +Date: Fri, 28 Jan 2022 18:33:46 +0100
> +Subject: [PATCH] Makefile: fix build with binutils 2.38
> +
> +From version 2.38, binutils default to ISA spec version 20191213. This
> +means that the csr read/write (csrr*/csrw*) instructions and fence.i
> +instruction has separated from the `I` extension, become two standalone
> +extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> +this causes the following build failure:
> +
> + CC lib/sbi/sbi_tlb.o
> +<<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages:
> +<<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i'
> +make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1
> +
> +The fix is to specify those extensions explicitly in -march. However as
> +older binutils version do not support this, we first need to detect
> +that.
> +
> +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> +Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> +Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> +Reviewed-by: Anup Patel <anup@brainfault.org>
> +---
> + Makefile | 9 ++++++++-
> + 1 file changed, 8 insertions(+), 1 deletion(-)
> +
> +diff --git a/Makefile b/Makefile
> +index d6f097d..a294f46 100644
> +--- a/Makefile
> ++++ b/Makefile
> +@@ -106,6 +106,9 @@ ifndef PLATFORM_RISCV_XLEN
> + endif
> + endif
> +
> ++# Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
> ++CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
> ++
> + # Setup list of objects.mk files
> + ifdef PLATFORM
> + platform-object-mks=$(shell if [ -d $(platform_src_dir)/ ]; then find $(platform_src_dir) -iname "objects.mk" | sort -r; fi)
> +@@ -157,7 +160,11 @@ ifndef PLATFORM_RISCV_ABI
> + endif
> + ifndef PLATFORM_RISCV_ISA
> + ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
> +- PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
> ++ ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y)
> ++ PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc_zicsr_zifencei
> ++ else
> ++ PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
> ++ endif
> + else
> + PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
> + endif
> +--
> +2.35.1
> +
> diff --git a/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb b/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
> index c25215be..f114cec9 100644
> --- a/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
> +++ b/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
> @@ -7,6 +7,7 @@ inherit dpkg
>
> SRC_URI = " \
> https://github.com/riscv/opensbi/archive/v${PV}.tar.gz;downloadfilename=opensbi-${PV}.tar.gz \
> + file://0001-Makefile-fix-build-with-binutils-2.38.patch \
> file://sifive-fu540-rules"
> SRC_URI[sha256sum] = "60f995cb3cd03e3cf5e649194d3395d0fe67499fd960a36cf7058a4efde686f0"
>
Maybe it's better to update the opensbi revision then.
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
next prev parent reply other threads:[~2022-09-01 11:21 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 4:51 [PATCH 0/2] Fix sid-ports riscv64 build Uladzimir Bely
2022-09-01 4:52 ` [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38 Uladzimir Bely
2022-09-01 11:26 ` Jan Kiszka
2022-09-01 4:52 ` [PATCH 2/2] opensbi-sifive-fu540: Fix " Uladzimir Bely
2022-09-01 11:21 ` Jan Kiszka [this message]
2022-09-01 8:21 ` [PATCH 0/2] Fix sid-ports riscv64 build Henning Schild
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