* [PATCH 0/2] Fix sid-ports riscv64 build
@ 2022-09-01 4:51 Uladzimir Bely
2022-09-01 4:52 ` [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38 Uladzimir Bely
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Uladzimir Bely @ 2022-09-01 4:51 UTC (permalink / raw)
To: isar-users
Sid-ports got newer version of binutils and this led to the broken
native riscv64 builds for linux-mainline and opensbi-sifive-fu540.
Here are backported patches from upstreams.
Alternative solution would be upgrading version of the packages in Isar
up to linux-mainline >= 5.17 and opensbi-sifive-fu540 >= 1.1.
Uladzimir Bely (2):
linux-mainline: Fix riscv64 build with binutils 2.38
opensbi-sifive-fu540: Fix build with binutils 2.38
...akefile-fix-build-with-binutils-2.38.patch | 58 +++++++++++++++++++
.../opensbi/opensbi-sifive-fu540_0.9.bb | 1 +
...1-riscv-fix-build-with-binutils-2.38.patch | 50 ++++++++++++++++
.../linux/linux-mainline_5.4.70.bb | 2 +
4 files changed, 111 insertions(+)
create mode 100644 meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
create mode 100644 meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38
2022-09-01 4:51 [PATCH 0/2] Fix sid-ports riscv64 build Uladzimir Bely
@ 2022-09-01 4:52 ` Uladzimir Bely
2022-09-01 11:26 ` Jan Kiszka
2022-09-01 4:52 ` [PATCH 2/2] opensbi-sifive-fu540: Fix " Uladzimir Bely
2022-09-01 8:21 ` [PATCH 0/2] Fix sid-ports riscv64 build Henning Schild
2 siblings, 1 reply; 6+ messages in thread
From: Uladzimir Bely @ 2022-09-01 4:52 UTC (permalink / raw)
To: isar-users
Backport of https://github.com/torvalds/linux/commit/6df2a016c0c8
from linux-5.17.
Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
---
...1-riscv-fix-build-with-binutils-2.38.patch | 50 +++++++++++++++++++
.../linux/linux-mainline_5.4.70.bb | 2 +
2 files changed, 52 insertions(+)
create mode 100644 meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
diff --git a/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
new file mode 100644
index 00000000..d0920e54
--- /dev/null
+++ b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
@@ -0,0 +1,50 @@
+From 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Wed, 26 Jan 2022 18:14:42 +0100
+Subject: [PATCH] riscv: fix build with binutils 2.38
+
+From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+ CC arch/riscv/kernel/vdso/vgettimeofday.o
+ <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
+ <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+ <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+ <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+ <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
+
+The fix is to specify those extensions explicitely in -march. However as
+older binutils version do not support this, we first need to detect
+that.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+---
+ arch/riscv/Makefile | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 8a107ed18b0d..7d81102cffd4 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
+ riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
+ riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
+ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
++riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
++
+ KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
+ KBUILD_AFLAGS += -march=$(riscv-march-y)
+
+--
+2.35.1
+
diff --git a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
index 644535e8..b1ae6e60 100644
--- a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
+++ b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
@@ -15,6 +15,8 @@ SRC_URI += " \
file://no-ubifs-fs.cfg \
file://no-root-nfs.cfg;apply=no"
+SRC_URI_append_riscv64 = " file://0001-riscv-fix-build-with-binutils-2.38.patch"
+
SRC_URI[sha256sum] = "c0b3d8085c5ba235df38b00b740e053659709e8a5ca21957a239f6bc22c45007"
S = "${WORKDIR}/linux-${ARCHIVE_VERSION}"
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] opensbi-sifive-fu540: Fix build with binutils 2.38
2022-09-01 4:51 [PATCH 0/2] Fix sid-ports riscv64 build Uladzimir Bely
2022-09-01 4:52 ` [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38 Uladzimir Bely
@ 2022-09-01 4:52 ` Uladzimir Bely
2022-09-01 11:21 ` Jan Kiszka
2022-09-01 8:21 ` [PATCH 0/2] Fix sid-ports riscv64 build Henning Schild
2 siblings, 1 reply; 6+ messages in thread
From: Uladzimir Bely @ 2022-09-01 4:52 UTC (permalink / raw)
To: isar-users
Backport of https://github.com/riscv-software-src/opensbi/commit/5d53b55
from opensbi-1.1.
Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
---
...akefile-fix-build-with-binutils-2.38.patch | 58 +++++++++++++++++++
.../opensbi/opensbi-sifive-fu540_0.9.bb | 1 +
2 files changed, 59 insertions(+)
create mode 100644 meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
diff --git a/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch b/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
new file mode 100644
index 00000000..d52a4695
--- /dev/null
+++ b/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
@@ -0,0 +1,58 @@
+From 5d53b55aa77ffeefd4012445dfa6ad3535e1ff2c Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 28 Jan 2022 18:33:46 +0100
+Subject: [PATCH] Makefile: fix build with binutils 2.38
+
+From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+ CC lib/sbi/sbi_tlb.o
+<<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages:
+<<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i'
+make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1
+
+The fix is to specify those extensions explicitly in -march. However as
+older binutils version do not support this, we first need to detect
+that.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Reviewed-by: Anup Patel <anup@brainfault.org>
+---
+ Makefile | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index d6f097d..a294f46 100644
+--- a/Makefile
++++ b/Makefile
+@@ -106,6 +106,9 @@ ifndef PLATFORM_RISCV_XLEN
+ endif
+ endif
+
++# Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
++CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
++
+ # Setup list of objects.mk files
+ ifdef PLATFORM
+ platform-object-mks=$(shell if [ -d $(platform_src_dir)/ ]; then find $(platform_src_dir) -iname "objects.mk" | sort -r; fi)
+@@ -157,7 +160,11 @@ ifndef PLATFORM_RISCV_ABI
+ endif
+ ifndef PLATFORM_RISCV_ISA
+ ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
+- PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
++ ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y)
++ PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc_zicsr_zifencei
++ else
++ PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
++ endif
+ else
+ PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
+ endif
+--
+2.35.1
+
diff --git a/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb b/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
index c25215be..f114cec9 100644
--- a/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
+++ b/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
@@ -7,6 +7,7 @@ inherit dpkg
SRC_URI = " \
https://github.com/riscv/opensbi/archive/v${PV}.tar.gz;downloadfilename=opensbi-${PV}.tar.gz \
+ file://0001-Makefile-fix-build-with-binutils-2.38.patch \
file://sifive-fu540-rules"
SRC_URI[sha256sum] = "60f995cb3cd03e3cf5e649194d3395d0fe67499fd960a36cf7058a4efde686f0"
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Fix sid-ports riscv64 build
2022-09-01 4:51 [PATCH 0/2] Fix sid-ports riscv64 build Uladzimir Bely
2022-09-01 4:52 ` [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38 Uladzimir Bely
2022-09-01 4:52 ` [PATCH 2/2] opensbi-sifive-fu540: Fix " Uladzimir Bely
@ 2022-09-01 8:21 ` Henning Schild
2 siblings, 0 replies; 6+ messages in thread
From: Henning Schild @ 2022-09-01 8:21 UTC (permalink / raw)
To: Uladzimir Bely; +Cc: isar-users
Am Thu, 1 Sep 2022 06:51:59 +0200
schrieb Uladzimir Bely <ubely@ilbers.de>:
> Sid-ports got newer version of binutils and this led to the broken
> native riscv64 builds for linux-mainline and opensbi-sifive-fu540.
>
> Here are backported patches from upstreams.
>
> Alternative solution would be upgrading version of the packages in
> Isar up to linux-mainline >= 5.17 and opensbi-sifive-fu540 >= 1.1.
I think that would be the better option. Why maintain those backports
and stay on old stuff?
Henning
>
> Uladzimir Bely (2):
> linux-mainline: Fix riscv64 build with binutils 2.38
> opensbi-sifive-fu540: Fix build with binutils 2.38
>
> ...akefile-fix-build-with-binutils-2.38.patch | 58
> +++++++++++++++++++ .../opensbi/opensbi-sifive-fu540_0.9.bb |
> 1 + ...1-riscv-fix-build-with-binutils-2.38.patch | 50
> ++++++++++++++++ .../linux/linux-mainline_5.4.70.bb | 2 +
> 4 files changed, 111 insertions(+)
> create mode 100644
> meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
> create mode 100644
> meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] opensbi-sifive-fu540: Fix build with binutils 2.38
2022-09-01 4:52 ` [PATCH 2/2] opensbi-sifive-fu540: Fix " Uladzimir Bely
@ 2022-09-01 11:21 ` Jan Kiszka
0 siblings, 0 replies; 6+ messages in thread
From: Jan Kiszka @ 2022-09-01 11:21 UTC (permalink / raw)
To: Uladzimir Bely, isar-users
On 01.09.22 06:52, Uladzimir Bely wrote:
> Backport of https://github.com/riscv-software-src/opensbi/commit/5d53b55
> from opensbi-1.1.
>
> Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
> ---
> ...akefile-fix-build-with-binutils-2.38.patch | 58 +++++++++++++++++++
> .../opensbi/opensbi-sifive-fu540_0.9.bb | 1 +
> 2 files changed, 59 insertions(+)
> create mode 100644 meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
>
> diff --git a/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch b/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
> new file mode 100644
> index 00000000..d52a4695
> --- /dev/null
> +++ b/meta-isar/recipes-bsp/opensbi/files/0001-Makefile-fix-build-with-binutils-2.38.patch
> @@ -0,0 +1,58 @@
> +From 5d53b55aa77ffeefd4012445dfa6ad3535e1ff2c Mon Sep 17 00:00:00 2001
> +From: Aurelien Jarno <aurelien@aurel32.net>
> +Date: Fri, 28 Jan 2022 18:33:46 +0100
> +Subject: [PATCH] Makefile: fix build with binutils 2.38
> +
> +From version 2.38, binutils default to ISA spec version 20191213. This
> +means that the csr read/write (csrr*/csrw*) instructions and fence.i
> +instruction has separated from the `I` extension, become two standalone
> +extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> +this causes the following build failure:
> +
> + CC lib/sbi/sbi_tlb.o
> +<<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages:
> +<<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i'
> +make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1
> +
> +The fix is to specify those extensions explicitly in -march. However as
> +older binutils version do not support this, we first need to detect
> +that.
> +
> +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> +Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> +Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> +Reviewed-by: Anup Patel <anup@brainfault.org>
> +---
> + Makefile | 9 ++++++++-
> + 1 file changed, 8 insertions(+), 1 deletion(-)
> +
> +diff --git a/Makefile b/Makefile
> +index d6f097d..a294f46 100644
> +--- a/Makefile
> ++++ b/Makefile
> +@@ -106,6 +106,9 @@ ifndef PLATFORM_RISCV_XLEN
> + endif
> + endif
> +
> ++# Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
> ++CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
> ++
> + # Setup list of objects.mk files
> + ifdef PLATFORM
> + platform-object-mks=$(shell if [ -d $(platform_src_dir)/ ]; then find $(platform_src_dir) -iname "objects.mk" | sort -r; fi)
> +@@ -157,7 +160,11 @@ ifndef PLATFORM_RISCV_ABI
> + endif
> + ifndef PLATFORM_RISCV_ISA
> + ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
> +- PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
> ++ ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y)
> ++ PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc_zicsr_zifencei
> ++ else
> ++ PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
> ++ endif
> + else
> + PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
> + endif
> +--
> +2.35.1
> +
> diff --git a/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb b/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
> index c25215be..f114cec9 100644
> --- a/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
> +++ b/meta-isar/recipes-bsp/opensbi/opensbi-sifive-fu540_0.9.bb
> @@ -7,6 +7,7 @@ inherit dpkg
>
> SRC_URI = " \
> https://github.com/riscv/opensbi/archive/v${PV}.tar.gz;downloadfilename=opensbi-${PV}.tar.gz \
> + file://0001-Makefile-fix-build-with-binutils-2.38.patch \
> file://sifive-fu540-rules"
> SRC_URI[sha256sum] = "60f995cb3cd03e3cf5e649194d3395d0fe67499fd960a36cf7058a4efde686f0"
>
Maybe it's better to update the opensbi revision then.
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38
2022-09-01 4:52 ` [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38 Uladzimir Bely
@ 2022-09-01 11:26 ` Jan Kiszka
0 siblings, 0 replies; 6+ messages in thread
From: Jan Kiszka @ 2022-09-01 11:26 UTC (permalink / raw)
To: Uladzimir Bely, isar-users
On 01.09.22 06:52, Uladzimir Bely wrote:
> Backport of https://github.com/torvalds/linux/commit/6df2a016c0c8
> from linux-5.17.
NACK. We need to update the kernel then, either to the latest 5.4.y if
that fixes it or to a newer LTS kernel that does. We don't want to
maintain patches here for this demo purpose.
Jan
>
> Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
> ---
> ...1-riscv-fix-build-with-binutils-2.38.patch | 50 +++++++++++++++++++
> .../linux/linux-mainline_5.4.70.bb | 2 +
> 2 files changed, 52 insertions(+)
> create mode 100644 meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
>
> diff --git a/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
> new file mode 100644
> index 00000000..d0920e54
> --- /dev/null
> +++ b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
> @@ -0,0 +1,50 @@
> +From 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 Mon Sep 17 00:00:00 2001
> +From: Aurelien Jarno <aurelien@aurel32.net>
> +Date: Wed, 26 Jan 2022 18:14:42 +0100
> +Subject: [PATCH] riscv: fix build with binutils 2.38
> +
> +From version 2.38, binutils default to ISA spec version 20191213. This
> +means that the csr read/write (csrr*/csrw*) instructions and fence.i
> +instruction has separated from the `I` extension, become two standalone
> +extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> +this causes the following build failure:
> +
> + CC arch/riscv/kernel/vdso/vgettimeofday.o
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> +
> +The fix is to specify those extensions explicitely in -march. However as
> +older binutils version do not support this, we first need to detect
> +that.
> +
> +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> +Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> +Cc: stable@vger.kernel.org
> +Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> +---
> + arch/riscv/Makefile | 6 ++++++
> + 1 file changed, 6 insertions(+)
> +
> +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> +index 8a107ed18b0d..7d81102cffd4 100644
> +--- a/arch/riscv/Makefile
> ++++ b/arch/riscv/Makefile
> +@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
> + riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
> + riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
> + riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
> ++
> ++# Newer binutils versions default to ISA spec version 20191213 which moves some
> ++# instructions from the I extension to the Zicsr and Zifencei extensions.
> ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
> ++riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
> ++
> + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
> + KBUILD_AFLAGS += -march=$(riscv-march-y)
> +
> +--
> +2.35.1
> +
> diff --git a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
> index 644535e8..b1ae6e60 100644
> --- a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
> +++ b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
> @@ -15,6 +15,8 @@ SRC_URI += " \
> file://no-ubifs-fs.cfg \
> file://no-root-nfs.cfg;apply=no"
>
> +SRC_URI_append_riscv64 = " file://0001-riscv-fix-build-with-binutils-2.38.patch"
> +
> SRC_URI[sha256sum] = "c0b3d8085c5ba235df38b00b740e053659709e8a5ca21957a239f6bc22c45007"
>
> S = "${WORKDIR}/linux-${ARCHIVE_VERSION}"
--
Siemens AG, Technology
Competence Center Embedded Linux
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-01 11:26 UTC | newest]
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2022-09-01 4:51 [PATCH 0/2] Fix sid-ports riscv64 build Uladzimir Bely
2022-09-01 4:52 ` [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38 Uladzimir Bely
2022-09-01 11:26 ` Jan Kiszka
2022-09-01 4:52 ` [PATCH 2/2] opensbi-sifive-fu540: Fix " Uladzimir Bely
2022-09-01 11:21 ` Jan Kiszka
2022-09-01 8:21 ` [PATCH 0/2] Fix sid-ports riscv64 build Henning Schild
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