[PATCH v2 2/7] starfive-visionfive2: package u-boot

[Felix Moessbauer <felix.moessbauer@siemens.com>]

This patch adds the u-boot firmware for the starfive visionfive2 board.
As the image is signed at build time, but verified at runtime, we get a
rather complex cross dependency chain around openssl. To not diverge
from the official visionfive2 BSP example, we keep the image signing.

Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
 ...x-offset-of-env-data-block-on-jh7110.patch | 30 +++++++
 ...iscv-Fix-build-against-binutils-2.38.patch | 55 ++++++++++++
 ...-opensbi-memory-range-in-device-tree.patch | 40 +++++++++
 ...upport-building-double-float-modules.patch | 89 +++++++++++++++++++
 ...five-visionfive2_2022.01-rc4+VF2-v2.8.0.bb | 38 ++++++++
 5 files changed, 252 insertions(+)
 create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch
 create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch
 create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch
 create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch
 create mode 100644 meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb

diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch
new file mode 100644
index 00000000..bc373ff6
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch
@@ -0,0 +1,30 @@
+From 3849b7fa6b35a5a1729c9d605d448d97862bcb5d Mon Sep 17 00:00:00 2001
+From: Felix Moessbauer <felix.moessbauer@siemens.com>
+Date: Fri, 27 Jan 2023 12:36:13 +0800
+Subject: [PATCH 1/2] fix offset of env data block on jh7110
+
+Xref: https://github.com/starfive-tech/u-boot/issues/39
+
+Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
+---
+ configs/starfive_visionfive2_defconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
+index 45c1767d34..032d208e77 100644
+--- a/configs/starfive_visionfive2_defconfig
++++ b/configs/starfive_visionfive2_defconfig
+@@ -1,8 +1,8 @@
+ CONFIG_RISCV=y
+ CONFIG_SYS_MALLOC_F_LEN=0x10000
+ CONFIG_NR_DRAM_BANKS=1
+-CONFIG_ENV_SIZE=0x10000
+-CONFIG_ENV_OFFSET=0xF0000
++CONFIG_ENV_SIZE=0x100000
++CONFIG_ENV_OFFSET=0xF00000
+ CONFIG_SPL_DM_SPI=y
+ CONFIG_DEFAULT_DEVICE_TREE="starfive_visionfive2"
+ CONFIG_SPL_MMC_SUPPORT=y
+-- 
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch
new file mode 100644
index 00000000..6f8a2ae0
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch
@@ -0,0 +1,55 @@
+From 5df4b2299f86933fa79aa3bc6a3986fc7e55b7e0 Mon Sep 17 00:00:00 2001
+From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Date: Mon, 3 Oct 2022 18:07:54 +0200
+Subject: [PATCH 1/2] riscv: Fix build against binutils 2.38
+
+The following description is copied from the equivalent patch for the
+Linux Kernel proposed by Aurelien Jarno:
+
+>From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+arch/riscv/cpu/mtrap.S: Assembler messages:
+arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
+arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
+arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
+arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
+
+Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Christian Stewart <christian@paral.in>
+Reviewed-by: Rick Chen <rick@andestech.com>
+---
+ arch/riscv/Makefile | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0b80eb8d86..53d1194ffb 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ 	CMODEL = medany
+ endif
+ 
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
++ifeq ($(toolchain-need-zicsr-zifencei),y)
++	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
++endif
++
++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
+ 	     -mcmodel=$(CMODEL)
+ 
+ PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)
+-- 
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch
new file mode 100644
index 00000000..0a19707f
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch
@@ -0,0 +1,40 @@
+From 0e037ddfc425ad716afb0120db8c6e92fe9a2802 Mon Sep 17 00:00:00 2001
+From: Felix Moessbauer <felix.moessbauer@siemens.com>
+Date: Mon, 30 Jan 2023 11:05:01 +0800
+Subject: [PATCH 2/2] exclude opensbi memory range in device tree
+
+This patch explicitly excludes the memory range of the OpenSBI in the
+built-in device tree. When booting EFI, the efi loader has to know
+about that zone before loading the device tree for Linux, otherwise
+it tries to access 0x40000000, leading to an access violation.
+
+Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
+---
+ arch/riscv/dts/starfive_visionfive2.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts
+index 4dcfa1bacb..9c1dce7363 100644
+--- a/arch/riscv/dts/starfive_visionfive2.dts
++++ b/arch/riscv/dts/starfive_visionfive2.dts
+@@ -34,6 +34,17 @@
+ 		reg = <0x0 0x40000000 0x1 0x0>;
+ 	};
+ 
++	reserved-memory {
++			#size-cells = <2>;
++			#address-cells = <2>;
++			ranges;
++
++			opensbi {
++				reg = <0x00 0x40000000 0x00 0x80000>;
++				no-map;
++			};
++	};
++
+ 	soc {
+ 	};
+ };
+-- 
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch
new file mode 100644
index 00000000..ec7d7d32
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch
@@ -0,0 +1,89 @@
+From 5aefdcad0950c244d826988a8bd2f90584399849 Mon Sep 17 00:00:00 2001
+From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Date: Wed, 12 Oct 2022 14:59:51 +0200
+Subject: [PATCH 2/2] riscv: support building double-float modules
+
+The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a
+compiled for double-float. To link to it we have to adjust how we build
+U-Boot.
+
+As U-Boot actually does not use floating point at all this should not
+make a significant difference for the produced binaries.
+
+Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Reviewed-by: Rick Chen <rick@andestech.com>
+Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
+---
+ arch/riscv/Kconfig  | 15 +++++++++++++++
+ arch/riscv/Makefile | 15 ++++++++++++---
+ 2 files changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
+index 0cf51799fe..25ed0ba1cf 100644
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -161,6 +161,21 @@ config RISCV_ISA_C
+ 	  when building U-Boot, which results in compressed instructions in the
+ 	  U-Boot binary.
+ 
++config RISCV_ISA_F
++	bool "Standard extension for Single-Precision Floating Point"
++	default y
++	help
++	  Adds "F" to the ISA string passed to the compiler.
++
++config RISCV_ISA_D
++	bool "Standard extension for Double-Precision Floating Point"
++	depends on RISCV_ISA_F
++	default y
++	help
++	  Adds "D" to the ISA string passed to the compiler and changes the
++	  riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
++	  lp64d.
++
+ config RISCV_ISA_A
+ 	def_bool y
+ 
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 53d1194ffb..4963b5109b 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -5,15 +5,22 @@
+ 
+ ifeq ($(CONFIG_ARCH_RV64I),y)
+ 	ARCH_BASE = rv64im
+-	ABI = lp64
++	ABI_BASE = lp64
+ endif
+ ifeq ($(CONFIG_ARCH_RV32I),y)
+ 	ARCH_BASE = rv32im
+-	ABI = ilp32
++	ABI_BASE = ilp32
+ endif
+ ifeq ($(CONFIG_RISCV_ISA_A),y)
+ 	ARCH_A = a
+ endif
++ifeq ($(CONFIG_RISCV_ISA_F),y)
++	ARCH_F = f
++endif
++ifeq ($(CONFIG_RISCV_ISA_D),y)
++	ARCH_D = d
++	ABI_D = d
++endif
+ ifeq ($(CONFIG_RISCV_ISA_C),y)
+ 	ARCH_C = c
+ endif
+@@ -24,7 +31,9 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ 	CMODEL = medany
+ endif
+ 
+-RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)
++ABI = $(ABI_BASE)$(ABI_D)
+ 
+ # Newer binutils versions default to ISA spec version 20191213 which moves some
+ # instructions from the I extension to the Zicsr and Zifencei extensions.
+-- 
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb b/meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb
new file mode 100644
index 00000000..0f8fdfe2
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb
@@ -0,0 +1,38 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+require recipes-bsp/u-boot/u-boot-custom.inc
+
+SRC_URI += " \
+    git://github.com/starfive-tech/u-boot.git;branch=JH7110_VisionFive2_devel;protocol=https;destsuffix=u-boot-${PV} \
+    file://starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch \
+    file://starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch \
+    file://starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch \
+    file://starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch \
+    "
+SRCREV = "f1d959f0b02e16842181a4c1723ba3ea30d2e04a"
+
+DEBIAN_BUILD_DEPENDS .= ", libssl-dev:${HOST_ARCH}, libssl-dev:${DISTRO_ARCH}"
+
+# TODO: analyze the strange cross gcc include chain
+DEBIAN_BUILD_DEPENDS .= ", libc6-dev-i386:${HOST_ARCH}"
+
+U_BOOT_CONFIG = "starfive_visionfive2_defconfig"
+U_BOOT_BIN = "u-boot.bin"
+U_BOOT_SPL_BIN = "spl/u-boot-spl.bin"
+
+S = "${WORKDIR}/u-boot-${PV}"
+
+# install dtb files for opensbi
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build:append() {
+    # also build and install spl component
+    sed -i 's|${U_BOOT_BIN}|${U_BOOT_BIN} ${U_BOOT_SPL_BIN}|g' ${S}/debian/rules
+    echo "${U_BOOT_SPL_BIN} usr/lib/u-boot/${MACHINE}/" \
+        >> ${S}/debian/u-boot-${MACHINE}.install
+    # install device tree
+    echo "arch/riscv/dts/*.dtb usr/share/u-boot/${MACHINE}/" \
+        >> ${S}/debian/u-boot-${MACHINE}-dev.install
+}
-- 
2.34.1