From: Uladzimir Bely <ubely@ilbers.de>
To: isar-users@googlegroups.com
Subject: [PATCH 2/2] testsuite: Add cross-build and run tests for riscv64 targets
Date: Thu, 24 Apr 2025 10:02:24 +0300 [thread overview]
Message-ID: <20250424070606.11003-3-ubely@ilbers.de> (raw)
In-Reply-To: <20250424070606.11003-1-ubely@ilbers.de>
Since stability of new riscv64 targets is not known yet, don't mark
complete CI as failed if some of new tests fail.
Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
---
meta-isar/conf/machine/qemuriscv64.conf | 2 +-
testsuite/citest.py | 35 +++++++++++++++++++++++++
testsuite/start_vm.py | 2 +-
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/meta-isar/conf/machine/qemuriscv64.conf b/meta-isar/conf/machine/qemuriscv64.conf
index 3f14727a..4cb4f371 100644
--- a/meta-isar/conf/machine/qemuriscv64.conf
+++ b/meta-isar/conf/machine/qemuriscv64.conf
@@ -21,7 +21,7 @@ QEMU_ROOTFS_DEV ?= "vda"
QEMU_ARCH ?= "riscv64"
QEMU_MACHINE ?= "virt"
-QEMU_CPU ?= "rv64gcsu-v1.10.0"
+QEMU_CPU ?= "rv64"
# TODO: start_vm doesn't support multiline vars
QEMU_DISK_ARGS ?= "-drive file=##ROOTFS_IMAGE##,if=none,format=raw,id=hd0 -device virtio-blk-device,drive=hd0"
diff --git a/testsuite/citest.py b/testsuite/citest.py
index 56ac1f52..1ba1de9f 100755
--- a/testsuite/citest.py
+++ b/testsuite/citest.py
@@ -204,6 +204,21 @@ class CrossTest(CIBaseTest):
self.init()
self.perform_build_test(targets)
+ def test_cross_riscv64(self):
+ """
+ :avocado: tags=riscv64
+ """
+ targets = [
+ 'mc:qemuriscv64-trixie:isar-image-ci',
+ 'mc:qemuriscv64-noble:isar-image-ci',
+ ]
+
+ self.init()
+ try:
+ self.perform_build_test(targets, cross=False)
+ except exceptions.TestFail:
+ self.cancel('KFAIL')
+
class WicTest(CIBaseTest):
@@ -563,6 +578,26 @@ class VmBootTestFast(CIBaseTest):
script='test_systemd_unit.sh getty.target 10',
)
+ def test_riscv64_trixie(self):
+ """
+ :avocado: tags=riscv64
+ """
+ self.init()
+ try:
+ self.vm_start('riscv64', 'trixie', image='isar-image-ci')
+ except exceptions.TestFail:
+ self.cancel('KFAIL')
+
+ def test_riscv64_noble(self):
+ """
+ :avocado: tags=riscv64
+ """
+ self.init()
+ try:
+ self.vm_start('riscv64', 'noble', image='isar-image-ci')
+ except exceptions.TestFail:
+ self.cancel('KFAIL')
+
class VmBootTestFull(CIBaseTest):
diff --git a/testsuite/start_vm.py b/testsuite/start_vm.py
index 57d169df..18c6139c 100755
--- a/testsuite/start_vm.py
+++ b/testsuite/start_vm.py
@@ -148,7 +148,7 @@ def start_qemu(arch, build, distro, image, out, pid, enforce_pcbios):
def parse_args():
parser = argparse.ArgumentParser()
- arch_names = ['arm', 'arm64', 'amd64', 'amd64-sb', 'amd64-cip', 'amd64-iso', 'i386', 'mipsel']
+ arch_names = ['arm', 'arm64', 'amd64', 'amd64-sb', 'amd64-cip', 'amd64-iso', 'i386', 'mipsel', 'riscv64']
distro_names = [
'buster',
'bullseye',
--
2.49.0
--
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prev parent reply other threads:[~2025-04-24 7:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-24 7:02 [PATCH 0/2] Add riscv64 support for Ubuntu Noble Uladzimir Bely
2025-04-24 7:02 ` [PATCH 1/2] meta-isar: Add ubuntu-ports riscv64 support in Isar Uladzimir Bely
2025-04-24 7:02 ` Uladzimir Bely [this message]
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