From: Anton Mikanovich <amikan@ilbers.de>
To: isar-users@googlegroups.com
Cc: Uladzimir Bely <ubely@ilbers.de>, Anton Mikanovich <amikan@ilbers.de>
Subject: [PATCH v2 2/2] testsuite: Add cross-build and run tests for riscv64 targets
Date: Mon,  3 Nov 2025 09:55:22 +0200	[thread overview]
Message-ID: <20251103075522.187102-3-amikan@ilbers.de> (raw)
In-Reply-To: <20251103075522.187102-1-amikan@ilbers.de>
From: Uladzimir Bely <ubely@ilbers.de>
Since stability of new riscv64 targets is not known yet, don't mark
complete CI as failed if some of new tests fail.
Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
Signed-off-by: Anton Mikanovich <amikan@ilbers.de>
---
 testsuite/citest.py   | 35 +++++++++++++++++++++++++++++++++++
 testsuite/start_vm.py |  2 +-
 2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/testsuite/citest.py b/testsuite/citest.py
index a1214e9c..f4ae5a72 100755
--- a/testsuite/citest.py
+++ b/testsuite/citest.py
@@ -255,6 +255,21 @@ class CrossTest(CIBaseTest):
         self.init()
         self.perform_build_test(targets)
 
+    def test_cross_riscv64(self):
+        """
+        :avocado: tags=riscv64
+        """
+        targets = [
+            'mc:qemuriscv64-trixie:isar-image-ci',
+            'mc:qemuriscv64-noble:isar-image-ci',
+        ]
+
+        self.init()
+        try:
+            self.perform_build_test(targets, cross=False)
+        except exceptions.TestFail:
+            self.cancel('KFAIL')
+
 
 class KernelTests(CIBaseTest):
     """
@@ -644,6 +659,26 @@ class VmBootTestFast(CIBaseTest):
         self.init()
         self.vm_start('arm64', 'trixie')
 
+    def test_riscv64_trixie(self):
+        """
+        :avocado: tags=riscv64
+        """
+        self.init()
+        try:
+            self.vm_start('riscv64', 'trixie', image='isar-image-ci')
+        except exceptions.TestFail:
+            self.cancel('KFAIL')
+
+    def test_riscv64_noble(self):
+        """
+        :avocado: tags=riscv64
+        """
+        self.init()
+        try:
+            self.vm_start('riscv64', 'noble', image='isar-image-ci')
+        except exceptions.TestFail:
+            self.cancel('KFAIL')
+
 
 class VmBootTestFull(CIBaseTest):
 
diff --git a/testsuite/start_vm.py b/testsuite/start_vm.py
index 57d169df..18c6139c 100755
--- a/testsuite/start_vm.py
+++ b/testsuite/start_vm.py
@@ -148,7 +148,7 @@ def start_qemu(arch, build, distro, image, out, pid, enforce_pcbios):
 
 def parse_args():
     parser = argparse.ArgumentParser()
-    arch_names = ['arm', 'arm64', 'amd64', 'amd64-sb', 'amd64-cip', 'amd64-iso', 'i386', 'mipsel']
+    arch_names = ['arm', 'arm64', 'amd64', 'amd64-sb', 'amd64-cip', 'amd64-iso', 'i386', 'mipsel', 'riscv64']
     distro_names = [
         'buster',
         'bullseye',
-- 
2.34.1
-- 
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     prev parent reply	other threads:[~2025-11-03  7:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03  7:55 [PATCH v2 0/2] Add riscv64 support for Ubuntu Noble Anton Mikanovich
2025-11-03  7:55 ` [PATCH v2 1/2] meta-isar: Add ubuntu-ports riscv64 support in Isar Anton Mikanovich
2025-11-03  7:55 ` Anton Mikanovich [this message]
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