From: Jan Kiszka <jan.kiszka@siemens.com>
To: Uladzimir Bely <ubely@ilbers.de>, <isar-users@googlegroups.com>
Subject: Re: [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38
Date: Thu, 1 Sep 2022 13:26:19 +0200 [thread overview]
Message-ID: <463b1d7f-e488-4e29-534f-d1f450d9e998@siemens.com> (raw)
In-Reply-To: <20220901045201.9294-2-ubely@ilbers.de>
On 01.09.22 06:52, Uladzimir Bely wrote:
> Backport of https://github.com/torvalds/linux/commit/6df2a016c0c8
> from linux-5.17.
NACK. We need to update the kernel then, either to the latest 5.4.y if
that fixes it or to a newer LTS kernel that does. We don't want to
maintain patches here for this demo purpose.
Jan
>
> Signed-off-by: Uladzimir Bely <ubely@ilbers.de>
> ---
> ...1-riscv-fix-build-with-binutils-2.38.patch | 50 +++++++++++++++++++
> .../linux/linux-mainline_5.4.70.bb | 2 +
> 2 files changed, 52 insertions(+)
> create mode 100644 meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
>
> diff --git a/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
> new file mode 100644
> index 00000000..d0920e54
> --- /dev/null
> +++ b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch
> @@ -0,0 +1,50 @@
> +From 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 Mon Sep 17 00:00:00 2001
> +From: Aurelien Jarno <aurelien@aurel32.net>
> +Date: Wed, 26 Jan 2022 18:14:42 +0100
> +Subject: [PATCH] riscv: fix build with binutils 2.38
> +
> +From version 2.38, binutils default to ISA spec version 20191213. This
> +means that the csr read/write (csrr*/csrw*) instructions and fence.i
> +instruction has separated from the `I` extension, become two standalone
> +extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> +this causes the following build failure:
> +
> + CC arch/riscv/kernel/vdso/vgettimeofday.o
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> + <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> +
> +The fix is to specify those extensions explicitely in -march. However as
> +older binutils version do not support this, we first need to detect
> +that.
> +
> +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> +Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> +Cc: stable@vger.kernel.org
> +Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> +---
> + arch/riscv/Makefile | 6 ++++++
> + 1 file changed, 6 insertions(+)
> +
> +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> +index 8a107ed18b0d..7d81102cffd4 100644
> +--- a/arch/riscv/Makefile
> ++++ b/arch/riscv/Makefile
> +@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
> + riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
> + riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
> + riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
> ++
> ++# Newer binutils versions default to ISA spec version 20191213 which moves some
> ++# instructions from the I extension to the Zicsr and Zifencei extensions.
> ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
> ++riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
> ++
> + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
> + KBUILD_AFLAGS += -march=$(riscv-march-y)
> +
> +--
> +2.35.1
> +
> diff --git a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
> index 644535e8..b1ae6e60 100644
> --- a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
> +++ b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb
> @@ -15,6 +15,8 @@ SRC_URI += " \
> file://no-ubifs-fs.cfg \
> file://no-root-nfs.cfg;apply=no"
>
> +SRC_URI_append_riscv64 = " file://0001-riscv-fix-build-with-binutils-2.38.patch"
> +
> SRC_URI[sha256sum] = "c0b3d8085c5ba235df38b00b740e053659709e8a5ca21957a239f6bc22c45007"
>
> S = "${WORKDIR}/linux-${ARCHIVE_VERSION}"
--
Siemens AG, Technology
Competence Center Embedded Linux
next prev parent reply other threads:[~2022-09-01 11:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 4:51 [PATCH 0/2] Fix sid-ports riscv64 build Uladzimir Bely
2022-09-01 4:52 ` [PATCH 1/2] linux-mainline: Fix riscv64 build with binutils 2.38 Uladzimir Bely
2022-09-01 11:26 ` Jan Kiszka [this message]
2022-09-01 4:52 ` [PATCH 2/2] opensbi-sifive-fu540: Fix " Uladzimir Bely
2022-09-01 11:21 ` Jan Kiszka
2022-09-01 8:21 ` [PATCH 0/2] Fix sid-ports riscv64 build Henning Schild
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