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X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2022 11:26:22.5464 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c5ca55d-0a91-4421-523a-08da8c0ccc96 X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=38ae3bcd-9579-4fd4-adda-b42e1495d55a;Ip=[194.138.21.74];Helo=[hybrid.siemens.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR01FT005.eop-EUR01.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB7426 X-TUID: ijiRSnTiHZtd On 01.09.22 06:52, Uladzimir Bely wrote: > Backport of https://github.com/torvalds/linux/commit/6df2a016c0c8 > from linux-5.17. NACK. We need to update the kernel then, either to the latest 5.4.y if that fixes it or to a newer LTS kernel that does. We don't want to maintain patches here for this demo purpose. Jan > > Signed-off-by: Uladzimir Bely > --- > ...1-riscv-fix-build-with-binutils-2.38.patch | 50 +++++++++++++++++++ > .../linux/linux-mainline_5.4.70.bb | 2 + > 2 files changed, 52 insertions(+) > create mode 100644 meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch > > diff --git a/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch > new file mode 100644 > index 00000000..d0920e54 > --- /dev/null > +++ b/meta-isar/recipes-kernel/linux/files/0001-riscv-fix-build-with-binutils-2.38.patch > @@ -0,0 +1,50 @@ > +From 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 Mon Sep 17 00:00:00 2001 > +From: Aurelien Jarno > +Date: Wed, 26 Jan 2022 18:14:42 +0100 > +Subject: [PATCH] riscv: fix build with binutils 2.38 > + > +From version 2.38, binutils default to ISA spec version 20191213. This > +means that the csr read/write (csrr*/csrw*) instructions and fence.i > +instruction has separated from the `I` extension, become two standalone > +extensions: Zicsr and Zifencei. As the kernel uses those instruction, > +this causes the following build failure: > + > + CC arch/riscv/kernel/vdso/vgettimeofday.o > + <>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: > + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' > + > +The fix is to specify those extensions explicitely in -march. However as > +older binutils version do not support this, we first need to detect > +that. > + > +Signed-off-by: Aurelien Jarno > +Tested-by: Alexandre Ghiti > +Cc: stable@vger.kernel.org > +Signed-off-by: Palmer Dabbelt > +--- > + arch/riscv/Makefile | 6 ++++++ > + 1 file changed, 6 insertions(+) > + > +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > +index 8a107ed18b0d..7d81102cffd4 100644 > +--- a/arch/riscv/Makefile > ++++ b/arch/riscv/Makefile > +@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > + riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > + riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd > + riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > ++ > ++# Newer binutils versions default to ISA spec version 20191213 which moves some > ++# instructions from the I extension to the Zicsr and Zifencei extensions. > ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > ++riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > ++ > + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > + KBUILD_AFLAGS += -march=$(riscv-march-y) > + > +-- > +2.35.1 > + > diff --git a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb > index 644535e8..b1ae6e60 100644 > --- a/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb > +++ b/meta-isar/recipes-kernel/linux/linux-mainline_5.4.70.bb > @@ -15,6 +15,8 @@ SRC_URI += " \ > file://no-ubifs-fs.cfg \ > file://no-root-nfs.cfg;apply=no" > > +SRC_URI_append_riscv64 = " file://0001-riscv-fix-build-with-binutils-2.38.patch" > + > SRC_URI[sha256sum] = "c0b3d8085c5ba235df38b00b740e053659709e8a5ca21957a239f6bc22c45007" > > S = "${WORKDIR}/linux-${ARCHIVE_VERSION}" -- Siemens AG, Technology Competence Center Embedded Linux