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[192.35.17.14]) by gmr-mx.google.com with ESMTPS id a35-v6si235962edd.1.2018.11.04.22.52.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 04 Nov 2018 22:52:14 -0800 (PST) Received-SPF: pass (google.com: domain of jan.kiszka@siemens.com designates 192.35.17.14 as permitted sender) client-ip=192.35.17.14; Authentication-Results: gmr-mx.google.com; spf=pass (google.com: domain of jan.kiszka@siemens.com designates 192.35.17.14 as permitted sender) smtp.mailfrom=jan.kiszka@siemens.com Received: from mail2.sbs.de (mail2.sbs.de [192.129.41.66]) by david.siemens.de (8.15.2/8.15.2) with ESMTPS id wA56qD2B007527 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 5 Nov 2018 07:52:13 +0100 Received: from md1f2u6c.ad001.siemens.net ([167.87.39.16]) by mail2.sbs.de (8.15.2/8.15.2) with ESMTP id wA56qBn3011680 for ; Mon, 5 Nov 2018 07:52:13 +0100 From: Jan Kiszka To: isar-users Subject: [PATCH 05/10] meta-isar: Add Terasic DE0-Nano-SoC as demonstration board Date: Mon, 5 Nov 2018 07:52:05 +0100 Message-Id: <80ea2325794f3365e91cb4dc96fad20a09960ced.1541400730.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 2.16.4 In-Reply-To: References: In-Reply-To: References: X-TUID: fwUxTwwFyFvB From: Jan Kiszka This requires to build a recent U-Boot release as well as a kernel with a DTB renaming patch so that U-Boot will find the corresponding device tree. Signed-off-by: Jan Kiszka --- meta-isar/conf/local.conf.sample | 1 + meta-isar/conf/machine/de0-nano-soc.conf | 18 ++++++++++ .../conf/multiconfig/de0-nano-soc-stretch.conf | 7 ++++ meta-isar/recipes-bsp/u-boot/u-boot_2018.09.bb | 11 ++++++ ...fpga-Rename-socfpga_cyclone5_de0_-sockit-.patch | 41 ++++++++++++++++++++++ .../recipes-kernel/linux/linux-mainline_4.19.0.bb | 3 ++ .../scripts/lib/wic/canned-wks/de0-nano-soc.wks | 10 ++++++ 7 files changed, 91 insertions(+) create mode 100644 meta-isar/conf/machine/de0-nano-soc.conf create mode 100644 meta-isar/conf/multiconfig/de0-nano-soc-stretch.conf create mode 100644 meta-isar/recipes-bsp/u-boot/u-boot_2018.09.bb create mode 100644 meta-isar/recipes-kernel/linux/files/0001-ARM-dts-socfpga-Rename-socfpga_cyclone5_de0_-sockit-.patch create mode 100644 meta-isar/scripts/lib/wic/canned-wks/de0-nano-soc.wks diff --git a/meta-isar/conf/local.conf.sample b/meta-isar/conf/local.conf.sample index 6a70d34..45de252 100644 --- a/meta-isar/conf/local.conf.sample +++ b/meta-isar/conf/local.conf.sample @@ -49,6 +49,7 @@ BBMULTICONFIG = " \ qemuamd64-jessie \ qemuamd64-stretch \ bananapi-stretch \ + de0-nano-soc-stretch \ qemuamd64-buster \ rpi-jessie \ " diff --git a/meta-isar/conf/machine/de0-nano-soc.conf b/meta-isar/conf/machine/de0-nano-soc.conf new file mode 100644 index 0000000..63b2cfb --- /dev/null +++ b/meta-isar/conf/machine/de0-nano-soc.conf @@ -0,0 +1,18 @@ +# +# Copyright (c) Siemens AG, 2018 +# +# SPDX-License-Identifier: MIT + +DISTRO_ARCH ?= "armhf" + +KERNEL_NAME ?= "mainline" + +U_BOOT_CONFIG_de0-nano-soc = "socfpga_de0_nano_soc_defconfig" +U_BOOT_BIN_de0-nano-soc = "u-boot-with-spl.sfp" + +IMAGE_TYPE ?= "wic-img" +WKS_FILE ?= "de0-nano-soc" +IMAGER_INSTALL += "u-boot-de0-nano-soc" +IMAGER_BUILD_DEPS += "u-boot-de0-nano-soc" + +IMAGE_INSTALL += "u-boot-tools u-boot-script" diff --git a/meta-isar/conf/multiconfig/de0-nano-soc-stretch.conf b/meta-isar/conf/multiconfig/de0-nano-soc-stretch.conf new file mode 100644 index 0000000..6882493 --- /dev/null +++ b/meta-isar/conf/multiconfig/de0-nano-soc-stretch.conf @@ -0,0 +1,7 @@ +# +# Copyright (c) Siemens AG, 2018 +# +# SPDX-License-Identifier: MIT + +MACHINE = "de0-nano-soc" +DISTRO = "debian-stretch" diff --git a/meta-isar/recipes-bsp/u-boot/u-boot_2018.09.bb b/meta-isar/recipes-bsp/u-boot/u-boot_2018.09.bb new file mode 100644 index 0000000..e0f756c --- /dev/null +++ b/meta-isar/recipes-bsp/u-boot/u-boot_2018.09.bb @@ -0,0 +1,11 @@ +# +# Copyright (c) Siemens AG, 2018 +# +# SPDX-License-Identifier: MIT + +require recipes-bsp/u-boot/u-boot-custom.inc + +SRC_URI += " \ + ftp://ftp.denx.de/pub/u-boot/u-boot-2018.09.tar.bz2 \ + " +SRC_URI[sha256sum] = "839bf23cfe8ce613a77e583a60375179d0ad324e92c82fbdd07bebf0fd142268" diff --git a/meta-isar/recipes-kernel/linux/files/0001-ARM-dts-socfpga-Rename-socfpga_cyclone5_de0_-sockit-.patch b/meta-isar/recipes-kernel/linux/files/0001-ARM-dts-socfpga-Rename-socfpga_cyclone5_de0_-sockit-.patch new file mode 100644 index 0000000..8eb602d --- /dev/null +++ b/meta-isar/recipes-kernel/linux/files/0001-ARM-dts-socfpga-Rename-socfpga_cyclone5_de0_-sockit-.patch @@ -0,0 +1,41 @@ +From 202eb5481421040e115526b75317b5ca72584806 Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Wed, 29 Aug 2018 17:15:04 +0200 +Subject: [PATCH] ARM: dts: socfpga: Rename + socfpga_cyclone5_de0_{sockit,nano_soc} + +Rename DT source for DE0 Nano SoC . The board name is really DE0-Nano-SoC +or Atlas SoC, and it is not to be confused with SoCkit board, which is a +different one. Rename the DT source file to match the board name and to +avoid this possible mixup with another different board. + +Signed-off-by: Marek Vasut +Cc: Dinh Nguyen +Cc: Jan Kiszka +Signed-off-by: Dinh Nguyen +--- + arch/arm/boot/dts/Makefile | 2 +- + ...ocfpga_cyclone5_de0_sockit.dts => socfpga_cyclone5_de0_nano_soc.dts} | 0 + 2 files changed, 1 insertion(+), 1 deletion(-) + rename arch/arm/boot/dts/{socfpga_cyclone5_de0_sockit.dts => socfpga_cyclone5_de0_nano_soc.dts} (100%) + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index b5bd3de87c33..1036d396da83 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -892,7 +892,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_mcvevk.dtb \ + socfpga_cyclone5_socdk.dtb \ +- socfpga_cyclone5_de0_sockit.dtb \ ++ socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sodia.dtb \ +diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +similarity index 100% +rename from arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts +rename to arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +-- +2.16.4 + diff --git a/meta-isar/recipes-kernel/linux/linux-mainline_4.19.0.bb b/meta-isar/recipes-kernel/linux/linux-mainline_4.19.0.bb index b109f3c..e50e149 100644 --- a/meta-isar/recipes-kernel/linux/linux-mainline_4.19.0.bb +++ b/meta-isar/recipes-kernel/linux/linux-mainline_4.19.0.bb @@ -14,6 +14,9 @@ SRC_URI += " \ file://x86_64_defconfig" SRC_URI[sha256sum] = "0c68f5655528aed4f99dae71a5b259edc93239fa899e2df79c055275c21749a1" +SRC_URI_append_de0-nano-soc = " \ + file://0001-ARM-dts-socfpga-Rename-socfpga_cyclone5_de0_-sockit-.patch" + S = "${WORKDIR}/linux-${ARCHIVE_VERSION}" KERNEL_DEFCONFIG_qemuamd64 = "x86_64_defconfig" diff --git a/meta-isar/scripts/lib/wic/canned-wks/de0-nano-soc.wks b/meta-isar/scripts/lib/wic/canned-wks/de0-nano-soc.wks new file mode 100644 index 0000000..993a4ca --- /dev/null +++ b/meta-isar/scripts/lib/wic/canned-wks/de0-nano-soc.wks @@ -0,0 +1,10 @@ +# +# Copyright (c) Siemens AG, 2018 +# +# SPDX-License-Identifier: MIT + +part --source rawcopy --sourceparams "file=/usr/lib/u-boot/de0-nano-soc/u-boot-with-spl.sfp" --system-id 0xa2 --align 1 + +part / --source rootfs --ondisk mmcblk0 --fstype ext4 --label platform --align 1024 --active + +bootloader --append "rw rootwait" -- 2.16.4