* [PATCH v2 1/7] u-boot: inject debian multi-arch config
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
@ 2023-02-11 9:21 ` Felix Moessbauer
2023-03-16 4:49 ` Uladzimir Bely
2023-02-11 9:21 ` [PATCH v2 2/7] starfive-visionfive2: package u-boot Felix Moessbauer
` (6 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Felix Moessbauer @ 2023-02-11 9:21 UTC (permalink / raw)
To: isar-users
Cc: jan.kiszka, daniel.bovensiepen, florian.bezdeka, jay.zhou,
Felix Moessbauer
For more complex u-boot configurations, correct debian multi-arch header
paths have to be set for both the host (~ISAR target) as well as the build
architecture (~ISAR host). In addition, the bits per long have to be set for
userspace ABI. For debian, this always corresponds to the
DEB_HOST_ARCH_BITS.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
meta/recipes-bsp/u-boot/files/debian/rules.tmpl | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/meta/recipes-bsp/u-boot/files/debian/rules.tmpl b/meta/recipes-bsp/u-boot/files/debian/rules.tmpl
index 806b01fe..be5b9877 100755
--- a/meta/recipes-bsp/u-boot/files/debian/rules.tmpl
+++ b/meta/recipes-bsp/u-boot/files/debian/rules.tmpl
@@ -12,6 +12,15 @@ export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)-
SET_CROSS_BUILD_TOOLS=CROSS_BUILD_TOOLS=y
endif
+# inject debian multi-arch include path
+KCFLAGS += -I/usr/include/$(DEB_HOST_MULTIARCH) -I/usr/$(DEB_HOST_MULTIARCH)/include
+HOSTCFLAGS += -I/usr/include/$(DEB_BUILD_MULTIARCH) -I/usr/$(DEB_BUILD_MULTIARCH)/include
+# define host architecture bitwidth
+KCFLAGS += -DBITS_PER_LONG=$(DEB_HOST_ARCH_BITS)
+
+export KCFLAGS
+export HOSTCFLAGS
+
override_dh_auto_build:
$(MAKE) $(PARALLEL_MAKE) ${U_BOOT_CONFIG}
$(MAKE) $(PARALLEL_MAKE) ${U_BOOT_BIN}
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/7] u-boot: inject debian multi-arch config
2023-02-11 9:21 ` [PATCH v2 1/7] u-boot: inject debian multi-arch config Felix Moessbauer
@ 2023-03-16 4:49 ` Uladzimir Bely
2023-03-16 7:33 ` Jan Kiszka
0 siblings, 1 reply; 12+ messages in thread
From: Uladzimir Bely @ 2023-03-16 4:49 UTC (permalink / raw)
To: isar-users, Felix Moessbauer
In the email from Saturday, 11 February 2023 12:21:46 +03 user Felix Moessbauer wrote:
> For more complex u-boot configurations, correct debian multi-arch header
> paths have to be set for both the host (~ISAR target) as well as the build
> architecture (~ISAR host). In addition, the bits per long have to be set for
> userspace ABI. For debian, this always corresponds to the
> DEB_HOST_ARCH_BITS.
>
> Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
> ---
> meta/recipes-bsp/u-boot/files/debian/rules.tmpl | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/meta/recipes-bsp/u-boot/files/debian/rules.tmpl b/meta/recipes-bsp/u-boot/files/debian/rules.tmpl
When running in CI, patch v1 causes build issues with u-boot on some armhf (at least) machines. A piece of `build/tmp/work/debian-bullseye-armhf/u-boot-stm32mp15x/2020.10-r0/temp/log.do_dpkg_build` log:
```
#
# configuration written to .config
#
make[2]: Leaving directory '/<<PKGBUILDDIR>>'
/usr/bin/make -j 8 u-boot.stm32
make[2]: Entering directory '/<<PKGBUILDDIR>>'
scripts/kconfig/conf --syncconfig Kconfig
UPD include/config.h
CFG u-boot.cfg
GEN include/autoconf.mk.dep
In file included from /usr/arm-linux-gnueabihf/include/features.h:485,
from /usr/arm-linux-gnueabihf/include/errno.h:25,
from ./include/common.h:17:
/usr/include/arm-linux-gnueabihf/gnu/stubs.h:7:11: fatal error: gnu/stubs-soft.h: No such file or directory
7 | # include <gnu/stubs-soft.h>
| ^~~~~~~~~~~~~~~~~~
compilation terminated.
In file included from /usr/arm-linux-gnueabihf/include/features.h:485,
from /usr/arm-linux-gnueabihf/include/errno.h:25,
from ./include/common.h:17:
/usr/include/arm-linux-gnueabihf/gnu/stubs.h:7:11: fatal error: gnu/stubs-soft.h: No such file or directory
7 | # include <gnu/stubs-soft.h>
| ^~~~~~~~~~~~~~~~~~
compilation terminated.
make[3]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
```
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/7] u-boot: inject debian multi-arch config
2023-03-16 4:49 ` Uladzimir Bely
@ 2023-03-16 7:33 ` Jan Kiszka
0 siblings, 0 replies; 12+ messages in thread
From: Jan Kiszka @ 2023-03-16 7:33 UTC (permalink / raw)
To: Uladzimir Bely, isar-users, Felix Moessbauer
On 16.03.23 05:49, Uladzimir Bely wrote:
> In the email from Saturday, 11 February 2023 12:21:46 +03 user Felix Moessbauer wrote:
>> For more complex u-boot configurations, correct debian multi-arch header
>> paths have to be set for both the host (~ISAR target) as well as the build
>> architecture (~ISAR host). In addition, the bits per long have to be set for
>> userspace ABI. For debian, this always corresponds to the
>> DEB_HOST_ARCH_BITS.
>>
>> Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
>> ---
>> meta/recipes-bsp/u-boot/files/debian/rules.tmpl | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/meta/recipes-bsp/u-boot/files/debian/rules.tmpl b/meta/recipes-bsp/u-boot/files/debian/rules.tmpl
>
> When running in CI, patch v1 causes build issues with u-boot on some armhf (at least) machines. A piece of `build/tmp/work/debian-bullseye-armhf/u-boot-stm32mp15x/2020.10-r0/temp/log.do_dpkg_build` log:
>
> ```
> #
> # configuration written to .config
> #
>
> make[2]: Leaving directory '/<<PKGBUILDDIR>>'
>
> /usr/bin/make -j 8 u-boot.stm32
>
> make[2]: Entering directory '/<<PKGBUILDDIR>>'
>
> scripts/kconfig/conf --syncconfig Kconfig
>
> UPD include/config.h
>
> CFG u-boot.cfg
>
> GEN include/autoconf.mk.dep
>
> In file included from /usr/arm-linux-gnueabihf/include/features.h:485,
> from /usr/arm-linux-gnueabihf/include/errno.h:25,
> from ./include/common.h:17:
> /usr/include/arm-linux-gnueabihf/gnu/stubs.h:7:11: fatal error: gnu/stubs-soft.h: No such file or directory
> 7 | # include <gnu/stubs-soft.h>
> | ^~~~~~~~~~~~~~~~~~
> compilation terminated.
> In file included from /usr/arm-linux-gnueabihf/include/features.h:485,
> from /usr/arm-linux-gnueabihf/include/errno.h:25,
> from ./include/common.h:17:
>
> /usr/include/arm-linux-gnueabihf/gnu/stubs.h:7:11: fatal error: gnu/stubs-soft.h: No such file or directory
> 7 | # include <gnu/stubs-soft.h>
> | ^~~~~~~~~~~~~~~~~~
> compilation terminated.
>
> make[3]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> ```
>
That refreshes my suspicion that we may only cater a special need of
this downstream U-Boot here, given how many other up- and downstream
trees we already built without this change.
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/7] starfive-visionfive2: package u-boot
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
2023-02-11 9:21 ` [PATCH v2 1/7] u-boot: inject debian multi-arch config Felix Moessbauer
@ 2023-02-11 9:21 ` Felix Moessbauer
2023-02-11 9:21 ` [PATCH v2 3/7] starfive-visionfive2: package opensbi firmware Felix Moessbauer
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-02-11 9:21 UTC (permalink / raw)
To: isar-users
Cc: jan.kiszka, daniel.bovensiepen, florian.bezdeka, jay.zhou,
Felix Moessbauer
This patch adds the u-boot firmware for the starfive visionfive2 board.
As the image is signed at build time, but verified at runtime, we get a
rather complex cross dependency chain around openssl. To not diverge
from the official visionfive2 BSP example, we keep the image signing.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
...x-offset-of-env-data-block-on-jh7110.patch | 30 +++++++
...iscv-Fix-build-against-binutils-2.38.patch | 55 ++++++++++++
...-opensbi-memory-range-in-device-tree.patch | 40 +++++++++
...upport-building-double-float-modules.patch | 89 +++++++++++++++++++
...five-visionfive2_2022.01-rc4+VF2-v2.8.0.bb | 38 ++++++++
5 files changed, 252 insertions(+)
create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch
create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch
create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch
create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch
create mode 100644 meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb
diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch
new file mode 100644
index 00000000..bc373ff6
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch
@@ -0,0 +1,30 @@
+From 3849b7fa6b35a5a1729c9d605d448d97862bcb5d Mon Sep 17 00:00:00 2001
+From: Felix Moessbauer <felix.moessbauer@siemens.com>
+Date: Fri, 27 Jan 2023 12:36:13 +0800
+Subject: [PATCH 1/2] fix offset of env data block on jh7110
+
+Xref: https://github.com/starfive-tech/u-boot/issues/39
+
+Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
+---
+ configs/starfive_visionfive2_defconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
+index 45c1767d34..032d208e77 100644
+--- a/configs/starfive_visionfive2_defconfig
++++ b/configs/starfive_visionfive2_defconfig
+@@ -1,8 +1,8 @@
+ CONFIG_RISCV=y
+ CONFIG_SYS_MALLOC_F_LEN=0x10000
+ CONFIG_NR_DRAM_BANKS=1
+-CONFIG_ENV_SIZE=0x10000
+-CONFIG_ENV_OFFSET=0xF0000
++CONFIG_ENV_SIZE=0x100000
++CONFIG_ENV_OFFSET=0xF00000
+ CONFIG_SPL_DM_SPI=y
+ CONFIG_DEFAULT_DEVICE_TREE="starfive_visionfive2"
+ CONFIG_SPL_MMC_SUPPORT=y
+--
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch
new file mode 100644
index 00000000..6f8a2ae0
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch
@@ -0,0 +1,55 @@
+From 5df4b2299f86933fa79aa3bc6a3986fc7e55b7e0 Mon Sep 17 00:00:00 2001
+From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Date: Mon, 3 Oct 2022 18:07:54 +0200
+Subject: [PATCH 1/2] riscv: Fix build against binutils 2.38
+
+The following description is copied from the equivalent patch for the
+Linux Kernel proposed by Aurelien Jarno:
+
+>From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+arch/riscv/cpu/mtrap.S: Assembler messages:
+arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
+arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
+arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
+arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
+
+Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Christian Stewart <christian@paral.in>
+Reviewed-by: Rick Chen <rick@andestech.com>
+---
+ arch/riscv/Makefile | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0b80eb8d86..53d1194ffb 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ CMODEL = medany
+ endif
+
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
++ifeq ($(toolchain-need-zicsr-zifencei),y)
++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
++endif
++
++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
+ -mcmodel=$(CMODEL)
+
+ PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
+--
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch
new file mode 100644
index 00000000..0a19707f
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch
@@ -0,0 +1,40 @@
+From 0e037ddfc425ad716afb0120db8c6e92fe9a2802 Mon Sep 17 00:00:00 2001
+From: Felix Moessbauer <felix.moessbauer@siemens.com>
+Date: Mon, 30 Jan 2023 11:05:01 +0800
+Subject: [PATCH 2/2] exclude opensbi memory range in device tree
+
+This patch explicitly excludes the memory range of the OpenSBI in the
+built-in device tree. When booting EFI, the efi loader has to know
+about that zone before loading the device tree for Linux, otherwise
+it tries to access 0x40000000, leading to an access violation.
+
+Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
+---
+ arch/riscv/dts/starfive_visionfive2.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts
+index 4dcfa1bacb..9c1dce7363 100644
+--- a/arch/riscv/dts/starfive_visionfive2.dts
++++ b/arch/riscv/dts/starfive_visionfive2.dts
+@@ -34,6 +34,17 @@
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
++ reserved-memory {
++ #size-cells = <2>;
++ #address-cells = <2>;
++ ranges;
++
++ opensbi {
++ reg = <0x00 0x40000000 0x00 0x80000>;
++ no-map;
++ };
++ };
++
+ soc {
+ };
+ };
+--
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch
new file mode 100644
index 00000000..ec7d7d32
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch
@@ -0,0 +1,89 @@
+From 5aefdcad0950c244d826988a8bd2f90584399849 Mon Sep 17 00:00:00 2001
+From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Date: Wed, 12 Oct 2022 14:59:51 +0200
+Subject: [PATCH 2/2] riscv: support building double-float modules
+
+The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a
+compiled for double-float. To link to it we have to adjust how we build
+U-Boot.
+
+As U-Boot actually does not use floating point at all this should not
+make a significant difference for the produced binaries.
+
+Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Reviewed-by: Rick Chen <rick@andestech.com>
+Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
+---
+ arch/riscv/Kconfig | 15 +++++++++++++++
+ arch/riscv/Makefile | 15 ++++++++++++---
+ 2 files changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
+index 0cf51799fe..25ed0ba1cf 100644
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -161,6 +161,21 @@ config RISCV_ISA_C
+ when building U-Boot, which results in compressed instructions in the
+ U-Boot binary.
+
++config RISCV_ISA_F
++ bool "Standard extension for Single-Precision Floating Point"
++ default y
++ help
++ Adds "F" to the ISA string passed to the compiler.
++
++config RISCV_ISA_D
++ bool "Standard extension for Double-Precision Floating Point"
++ depends on RISCV_ISA_F
++ default y
++ help
++ Adds "D" to the ISA string passed to the compiler and changes the
++ riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
++ lp64d.
++
+ config RISCV_ISA_A
+ def_bool y
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 53d1194ffb..4963b5109b 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -5,15 +5,22 @@
+
+ ifeq ($(CONFIG_ARCH_RV64I),y)
+ ARCH_BASE = rv64im
+- ABI = lp64
++ ABI_BASE = lp64
+ endif
+ ifeq ($(CONFIG_ARCH_RV32I),y)
+ ARCH_BASE = rv32im
+- ABI = ilp32
++ ABI_BASE = ilp32
+ endif
+ ifeq ($(CONFIG_RISCV_ISA_A),y)
+ ARCH_A = a
+ endif
++ifeq ($(CONFIG_RISCV_ISA_F),y)
++ ARCH_F = f
++endif
++ifeq ($(CONFIG_RISCV_ISA_D),y)
++ ARCH_D = d
++ ABI_D = d
++endif
+ ifeq ($(CONFIG_RISCV_ISA_C),y)
+ ARCH_C = c
+ endif
+@@ -24,7 +31,9 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ CMODEL = medany
+ endif
+
+-RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)
++ABI = $(ABI_BASE)$(ABI_D)
+
+ # Newer binutils versions default to ISA spec version 20191213 which moves some
+ # instructions from the I extension to the Zicsr and Zifencei extensions.
+--
+2.30.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb b/meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb
new file mode 100644
index 00000000..0f8fdfe2
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb
@@ -0,0 +1,38 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+require recipes-bsp/u-boot/u-boot-custom.inc
+
+SRC_URI += " \
+ git://github.com/starfive-tech/u-boot.git;branch=JH7110_VisionFive2_devel;protocol=https;destsuffix=u-boot-${PV} \
+ file://starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch \
+ file://starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch \
+ file://starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch \
+ file://starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch \
+ "
+SRCREV = "f1d959f0b02e16842181a4c1723ba3ea30d2e04a"
+
+DEBIAN_BUILD_DEPENDS .= ", libssl-dev:${HOST_ARCH}, libssl-dev:${DISTRO_ARCH}"
+
+# TODO: analyze the strange cross gcc include chain
+DEBIAN_BUILD_DEPENDS .= ", libc6-dev-i386:${HOST_ARCH}"
+
+U_BOOT_CONFIG = "starfive_visionfive2_defconfig"
+U_BOOT_BIN = "u-boot.bin"
+U_BOOT_SPL_BIN = "spl/u-boot-spl.bin"
+
+S = "${WORKDIR}/u-boot-${PV}"
+
+# install dtb files for opensbi
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build:append() {
+ # also build and install spl component
+ sed -i 's|${U_BOOT_BIN}|${U_BOOT_BIN} ${U_BOOT_SPL_BIN}|g' ${S}/debian/rules
+ echo "${U_BOOT_SPL_BIN} usr/lib/u-boot/${MACHINE}/" \
+ >> ${S}/debian/u-boot-${MACHINE}.install
+ # install device tree
+ echo "arch/riscv/dts/*.dtb usr/share/u-boot/${MACHINE}/" \
+ >> ${S}/debian/u-boot-${MACHINE}-dev.install
+}
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 3/7] starfive-visionfive2: package opensbi firmware
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
2023-02-11 9:21 ` [PATCH v2 1/7] u-boot: inject debian multi-arch config Felix Moessbauer
2023-02-11 9:21 ` [PATCH v2 2/7] starfive-visionfive2: package u-boot Felix Moessbauer
@ 2023-02-11 9:21 ` Felix Moessbauer
2023-02-13 6:39 ` Moessbauer, Felix
2023-02-11 9:21 ` [PATCH v2 4/7] starfive-visionfive2: add BSP kernel Felix Moessbauer
` (4 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Felix Moessbauer @ 2023-02-11 9:21 UTC (permalink / raw)
To: isar-users
Cc: jan.kiszka, daniel.bovensiepen, florian.bezdeka, jay.zhou,
Felix Moessbauer
This patch adds the opensbi firmware for the starfive visionfive2 board,
based on the official BSP package.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
.../files/starfive-visionfive2-rules.tmpl | 17 ++++++++++
...ensbi-starfive-visionfive2_1.2+20230107.bb | 31 +++++++++++++++++++
2 files changed, 48 insertions(+)
create mode 100644 meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl
create mode 100644 meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb
diff --git a/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl b/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl
new file mode 100644
index 00000000..5f35c1c2
--- /dev/null
+++ b/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl
@@ -0,0 +1,17 @@
+#!/usr/bin/make -f
+
+ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
+export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)-
+endif
+
+UBOOT_DTB_FILE := /usr/share/u-boot/starfive-visionfive2/${DTB_UBOOT_JH7110_VF2}
+FW_TEXT_START := 0x40000000
+
+override_dh_auto_build:
+ CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \
+ FW_PAYLOAD_PATH=/usr/lib/u-boot/starfive-visionfive2/u-boot.bin \
+ FW_FDT_PATH=$(UBOOT_DTB_FILE) \
+ FW_TEXT_START=$(FW_TEXT_START)
+
+%:
+ dh $@
diff --git a/meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb b/meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb
new file mode 100644
index 00000000..e7d767c9
--- /dev/null
+++ b/meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb
@@ -0,0 +1,31 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+inherit dpkg
+
+DESCRIPTION = "OpenSBI firmware for StarFive VisionFive 2"
+
+SRC_URI = " \
+ git://github.com/riscv-software-src/opensbi.git;destsuffix=opensbi-${PV};protocol=https;branch=master \
+ file://starfive-visionfive2-rules.tmpl"
+# required patches are not yet part of a release, but will be in 1.3
+SRCREV = "c8ea836ee33eb778f48f780412e147386dac5301"
+
+S = "${WORKDIR}/opensbi-${PV}"
+TEMPLATE_FILES += "starfive-visionfive2-rules.tmpl"
+TEMPLATE_VARS += "DTB_UBOOT_JH7110_VF2"
+
+DEPENDS = "u-boot-starfive-visionfive2"
+DEBIAN_BUILD_DEPENDS = " \
+ u-boot-starfive-visionfive2, \
+ u-boot-starfive-visionfive2-dev"
+
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build() {
+ cp ${WORKDIR}/starfive-visionfive2-rules ${WORKDIR}/rules
+ deb_debianize
+
+ echo "build/platform/generic/firmware/fw_payload.bin /usr/lib/opensbi/starfive-visionfive2/" > ${S}/debian/install
+}
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/7] starfive-visionfive2: package opensbi firmware
2023-02-11 9:21 ` [PATCH v2 3/7] starfive-visionfive2: package opensbi firmware Felix Moessbauer
@ 2023-02-13 6:39 ` Moessbauer, Felix
0 siblings, 0 replies; 12+ messages in thread
From: Moessbauer, Felix @ 2023-02-13 6:39 UTC (permalink / raw)
To: isar-users
Cc: Bovensiepen, Daniel (bovi), Bezdeka, Florian, Kiszka, Jan, jay.zhou
On Sat, 2023-02-11 at 09:21 +0000, Felix Moessbauer wrote:
> This patch adds the opensbi firmware for the starfive visionfive2
> board,
> based on the official BSP package.
>
> Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
> ---
> .../files/starfive-visionfive2-rules.tmpl | 17 ++++++++++
> ...ensbi-starfive-visionfive2_1.2+20230107.bb | 31
> +++++++++++++++++++
> 2 files changed, 48 insertions(+)
> create mode 100644 meta-isar/recipes-bsp/opensbi/files/starfive-
> visionfive2-rules.tmpl
> create mode 100644 meta-isar/recipes-bsp/opensbi/opensbi-starfive-
> visionfive2_1.2+20230107.bb
>
> diff --git a/meta-isar/recipes-bsp/opensbi/files/starfive-
> visionfive2-rules.tmpl b/meta-isar/recipes-
> bsp/opensbi/files/starfive-visionfive2-rules.tmpl
> new file mode 100644
> index 00000000..5f35c1c2
> --- /dev/null
> +++ b/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-
> rules.tmpl
> @@ -0,0 +1,17 @@
> +#!/usr/bin/make -f
> +
> +ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
> +export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)-
> +endif
> +
> +UBOOT_DTB_FILE := /usr/share/u-boot/starfive-
> visionfive2/${DTB_UBOOT_JH7110_VF2}
> +FW_TEXT_START := 0x40000000
> +
> +override_dh_auto_build:
> + CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \
> + FW_PAYLOAD_PATH=/usr/lib/u-boot/starfive-
> visionfive2/u-boot.bin \
> + FW_FDT_PATH=$(UBOOT_DTB_FILE) \
> + FW_TEXT_START=$(FW_TEXT_START)
> +
> +%:
> + dh $@
> diff --git a/meta-isar/recipes-bsp/opensbi/opensbi-starfive-
> visionfive2_1.2+20230107.bb b/meta-isar/recipes-bsp/opensbi/opensbi-
> starfive-visionfive2_1.2+20230107.bb
> new file mode 100644
> index 00000000..e7d767c9
> --- /dev/null
> +++ b/meta-isar/recipes-bsp/opensbi/opensbi-starfive-
> visionfive2_1.2+20230107.bb
> @@ -0,0 +1,31 @@
> +#
> +# Copyright (c) Siemens AG, 2023
> +#
> +# SPDX-License-Identifier: MIT
> +
> +inherit dpkg
> +
> +DESCRIPTION = "OpenSBI firmware for StarFive VisionFive 2"
> +
> +SRC_URI = " \
> + git://github.com/riscv-software-
> src/opensbi.git;destsuffix=opensbi-${PV};protocol=https;branch=master
> \
> + file://starfive-visionfive2-rules.tmpl"
> +# required patches are not yet part of a release, but will be in 1.3
> +SRCREV = "c8ea836ee33eb778f48f780412e147386dac5301"
Recently more things got integrated into the upstream OpenSBI.
The latest SHA1 is 65c2190b47b14341dac9f763fed2d4ecbbff2a69.
Will update it in a v3, but for now, please manually update that
revision in the bb recipe when testing.
Felix
> +
> +S = "${WORKDIR}/opensbi-${PV}"
> +TEMPLATE_FILES += "starfive-visionfive2-rules.tmpl"
> +TEMPLATE_VARS += "DTB_UBOOT_JH7110_VF2"
> +
> +DEPENDS = "u-boot-starfive-visionfive2"
> +DEBIAN_BUILD_DEPENDS = " \
> + u-boot-starfive-visionfive2, \
> + u-boot-starfive-visionfive2-dev"
> +
> +do_prepare_build[cleandirs] += "${S}/debian"
> +do_prepare_build() {
> + cp ${WORKDIR}/starfive-visionfive2-rules ${WORKDIR}/rules
> + deb_debianize
> +
> + echo "build/platform/generic/firmware/fw_payload.bin
> /usr/lib/opensbi/starfive-visionfive2/" > ${S}/debian/install
> +}
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/7] starfive-visionfive2: add BSP kernel
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
` (2 preceding siblings ...)
2023-02-11 9:21 ` [PATCH v2 3/7] starfive-visionfive2: package opensbi firmware Felix Moessbauer
@ 2023-02-11 9:21 ` Felix Moessbauer
2023-02-11 9:21 ` [PATCH v2 5/7] starfive-visionfive2: create u-boot-spl firmware Felix Moessbauer
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-02-11 9:21 UTC (permalink / raw)
To: isar-users
Cc: jan.kiszka, daniel.bovensiepen, florian.bezdeka, jay.zhou,
Felix Moessbauer
This patch adds the kernel (including configuration) from the
SDK package. To make this kernel build on gcc12, we add a patch
that fixes the machine model.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
...or-unrecognized-opcode-csrr-a5-0xc01.patch | 26 +++++++++++++++++++
| 3 +++
.../linux/linux-starfive_5.15-visionfive2.bb | 18 +++++++++++++
3 files changed, 47 insertions(+)
create mode 100644 meta-isar/recipes-kernel/linux/files/fix-Error-unrecognized-opcode-csrr-a5-0xc01.patch
create mode 100644 meta-isar/recipes-kernel/linux/files/starfive2_extra.cfg
create mode 100644 meta-isar/recipes-kernel/linux/linux-starfive_5.15-visionfive2.bb
diff --git a/meta-isar/recipes-kernel/linux/files/fix-Error-unrecognized-opcode-csrr-a5-0xc01.patch b/meta-isar/recipes-kernel/linux/files/fix-Error-unrecognized-opcode-csrr-a5-0xc01.patch
new file mode 100644
index 00000000..b4dcaf0d
--- /dev/null
+++ b/meta-isar/recipes-kernel/linux/files/fix-Error-unrecognized-opcode-csrr-a5-0xc01.patch
@@ -0,0 +1,26 @@
+From 2f75442523e4b44bdea4ae5bc2e95137d0303c8b Mon Sep 17 00:00:00 2001
+From: LIChengGang <43427321+Zeno-sole@users.noreply.github.com>
+Date: Thu, 12 Jan 2023 10:52:05 +0800
+Subject: [PATCH] fix: Error unrecognized opcode `csrr a5,0xc01
+
+---
+ arch/riscv/Makefile | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0eb4568fbd290..c18d87212177b 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -52,6 +52,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
+ riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
+ riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
+ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
++riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
++
+ KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
+ KBUILD_AFLAGS += -march=$(riscv-march-y)
+
--git a/meta-isar/recipes-kernel/linux/files/starfive2_extra.cfg b/meta-isar/recipes-kernel/linux/files/starfive2_extra.cfg
new file mode 100644
index 00000000..d11c28de
--- /dev/null
+++ b/meta-isar/recipes-kernel/linux/files/starfive2_extra.cfg
@@ -0,0 +1,3 @@
+# additional configuration to support stock debian userlands
+CONFIG_BINFMT_MISC=y
+CONFIG_SQUASHFS=m
diff --git a/meta-isar/recipes-kernel/linux/linux-starfive_5.15-visionfive2.bb b/meta-isar/recipes-kernel/linux/linux-starfive_5.15-visionfive2.bb
new file mode 100644
index 00000000..8f1d0a81
--- /dev/null
+++ b/meta-isar/recipes-kernel/linux/linux-starfive_5.15-visionfive2.bb
@@ -0,0 +1,18 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+require recipes-kernel/linux/linux-custom.inc
+
+SRC_URI += " \
+ git://github.com/starfive-tech/linux.git;protocol=https;branch=JH7110_VisionFive2_devel;destsuffix=linux-visionfive-${PV} \
+ file://fix-Error-unrecognized-opcode-csrr-a5-0xc01.patch \
+ file://starfive2_extra.cfg"
+SRCREV = "59cf9af678dbfa3d73f6cb86ed1ae7219da9f5c9"
+
+S = "${WORKDIR}/linux-visionfive-${PV}"
+
+KERNEL_DEFCONFIG = "starfive_visionfive2_defconfig"
+
+LINUX_VERSION_EXTENSION = "-isar"
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 5/7] starfive-visionfive2: create u-boot-spl firmware
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
` (3 preceding siblings ...)
2023-02-11 9:21 ` [PATCH v2 4/7] starfive-visionfive2: add BSP kernel Felix Moessbauer
@ 2023-02-11 9:21 ` Felix Moessbauer
2023-02-11 9:21 ` [PATCH v2 6/7] starfive-visionfive2: create u-boot-spl FIT image Felix Moessbauer
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-02-11 9:21 UTC (permalink / raw)
To: isar-users
Cc: jan.kiszka, daniel.bovensiepen, florian.bezdeka, jay.zhou,
Felix Moessbauer
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
.../jh7110-u-boot-spl-image/files/install | 1 +
.../jh7110-u-boot-spl-image/files/rules | 13 ++++++++
.../jh7110-u-boot-spl-image_0.1.bb | 30 +++++++++++++++++++
.../jh7110-u-boot-spl-tool_0.1.bb | 23 ++++++++++++++
4 files changed, 67 insertions(+)
create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/install
create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/rules
create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-image/jh7110-u-boot-spl-image_0.1.bb
create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-tool/jh7110-u-boot-spl-tool_0.1.bb
diff --git a/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/install b/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/install
new file mode 100644
index 00000000..c300f842
--- /dev/null
+++ b/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/install
@@ -0,0 +1 @@
+u-boot-spl.bin.normal.out usr/share/jh7110-uboot-spl-image
diff --git a/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/rules b/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/rules
new file mode 100644
index 00000000..3c28b2c0
--- /dev/null
+++ b/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/rules
@@ -0,0 +1,13 @@
+#!/usr/bin/make -f
+
+U_BOOT_SPL_BIN := /usr/lib/u-boot/starfive-visionfive2/u-boot-spl.bin
+# taken from https://github.com/starfive-tech/Tools
+OFFSET := 0x01010101
+
+override_dh_auto_build:
+ cp $(U_BOOT_SPL_BIN) u-boot-spl.bin
+ /usr/lib/jh7110-uboot-spl-tool/jh7110_uboot_spl u-boot-spl.bin $(OFFSET)
+ mv u-boot-spl.bin.out u-boot-spl.bin.normal.out
+
+%:
+ dh \$@
diff --git a/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/jh7110-u-boot-spl-image_0.1.bb b/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/jh7110-u-boot-spl-image_0.1.bb
new file mode 100644
index 00000000..08c53b51
--- /dev/null
+++ b/meta-isar/recipes-bsp/jh7110-u-boot-spl-image/jh7110-u-boot-spl-image_0.1.bb
@@ -0,0 +1,30 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+inherit dpkg
+
+SRC_URI = "file://rules file://install"
+
+DESCRIPTION = "StarFive VisionFive 2 u-boot SPL"
+DEPENDS = "jh7110-u-boot-spl-tool u-boot-starfive-visionfive2"
+DEBIAN_BUILD_DEPENDS = "jh7110-u-boot-spl-tool, u-boot-starfive-visionfive2:${DISTRO_ARCH}"
+
+# this is a host tool
+PACKAGE_ARCH = "${HOST_ARCH}"
+
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build(){
+ deb_debianize
+ cp ${WORKDIR}/install ${S}/debian/
+}
+
+do_deploy() {
+ dpkg --fsys-tarfile ${WORKDIR}/jh7110-u-boot-spl-image_${PV}*.deb | \
+ tar xOf - "./usr/share/jh7110-uboot-spl-image/u-boot-spl.bin.normal.out" \
+ > "${DEPLOY_DIR_IMAGE}/u-boot-spl.bin.normal.out"
+}
+
+addtask deploy after do_dpkg_build before do_build
+do_deploy[dirs] = "${DEPLOY_DIR_IMAGE}"
diff --git a/meta-isar/recipes-bsp/jh7110-u-boot-spl-tool/jh7110-u-boot-spl-tool_0.1.bb b/meta-isar/recipes-bsp/jh7110-u-boot-spl-tool/jh7110-u-boot-spl-tool_0.1.bb
new file mode 100644
index 00000000..1991e61a
--- /dev/null
+++ b/meta-isar/recipes-bsp/jh7110-u-boot-spl-tool/jh7110-u-boot-spl-tool_0.1.bb
@@ -0,0 +1,23 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+inherit dpkg
+
+DESCRIPTION = "replacement for proprietary VisionFive2 SDK spl_tool"
+LICENSE = "CPL-1"
+
+SRC_URI = "git://github.com/electrorys/jh7110_uboot_spl.git;branch=master;protocol=https;destsuffix=jh7110-uboot-spl"
+SRCREV = "e089116b902240659c1dcd6cbb6537dc4c1e316c"
+
+S = "${WORKDIR}/jh7110-uboot-spl"
+
+# This is a host tool
+PACKAGE_ARCH = "${HOST_ARCH}"
+
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build(){
+ deb_debianize
+ echo "jh7110_uboot_spl usr/lib/jh7110-uboot-spl-tool" > ${S}/debian/${PN}.install
+}
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 6/7] starfive-visionfive2: create u-boot-spl FIT image
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
` (4 preceding siblings ...)
2023-02-11 9:21 ` [PATCH v2 5/7] starfive-visionfive2: create u-boot-spl firmware Felix Moessbauer
@ 2023-02-11 9:21 ` Felix Moessbauer
2023-02-11 9:21 ` [PATCH v2 7/7] starfive-visionfive2: add machine Felix Moessbauer
2023-03-14 15:31 ` [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Schaffner, Tobias
7 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-02-11 9:21 UTC (permalink / raw)
To: isar-users
Cc: jan.kiszka, daniel.bovensiepen, florian.bezdeka, jay.zhou,
Felix Moessbauer
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
.../files/rules.tmpl | 12 ++++++
.../files/visionfive2-u-boot-firmware.install | 1 +
.../visionfive2-uboot-fit-image.its.tmpl | 41 +++++++++++++++++++
.../visionfive2-u-boot-firmware.bb | 36 ++++++++++++++++
4 files changed, 90 insertions(+)
create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/rules.tmpl
create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-u-boot-firmware.install
create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-uboot-fit-image.its.tmpl
create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/visionfive2-u-boot-firmware.bb
diff --git a/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/rules.tmpl b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/rules.tmpl
new file mode 100644
index 00000000..4826f7d6
--- /dev/null
+++ b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/rules.tmpl
@@ -0,0 +1,12 @@
+#!/usr/bin/make -f
+
+KERNEL_VERSION=$(shell find /usr/lib/ -maxdepth 1 -type d -name 'linux-image-*' | head -1 | sed 's/.*linux-image-//g')
+
+override_dh_auto_configure:
+ sed -i 's|<KERNEL_VERSION>|$(KERNEL_VERSION)|g' visionfive2-uboot-fit-image.its
+
+override_dh_auto_build:
+ mkimage -A riscv -O u-boot -f ${IMAGE_ITS_FILE} visionfive2_fw_payload.img
+
+%:
+ dh $@
diff --git a/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-u-boot-firmware.install b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-u-boot-firmware.install
new file mode 100644
index 00000000..d1bdf6d6
--- /dev/null
+++ b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-u-boot-firmware.install
@@ -0,0 +1 @@
+visionfive2_fw_payload.img usr/share/visionfive2-u-boot-firmware
diff --git a/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-uboot-fit-image.its.tmpl b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-uboot-fit-image.its.tmpl
new file mode 100644
index 00000000..4cbe9318
--- /dev/null
+++ b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-uboot-fit-image.its.tmpl
@@ -0,0 +1,41 @@
+/dts-v1/;
+
+/ {
+ description = "U-boot-spl FIT image for JH7110 VisionFive2";
+ #address-cells = <2>;
+
+ images {
+ firmware {
+ description = "u-boot";
+ data = /incbin/("/usr/lib/opensbi/starfive-visionfive2/fw_payload.bin");
+ type = "firmware";
+ arch = "riscv";
+ os = "u-boot";
+ load = <0x0 0x40000000>;
+ entry = <0x0 0x40000000>;
+ compression = "none";
+ };
+ fdt {
+ description = "DTB";
+ data = /incbin/("/usr/lib/linux-image-<KERNEL_VERSION>/${DTB_FILES}");
+ type = "flat_dt";
+ arch = "riscv";
+ compression = "none";
+ load = <0x46000000>;
+ entry = <0x46000000>;
+ hash {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ default = "config-1";
+
+ config-1 {
+ description = "U-boot-spl FIT config for JH7110 VisionFive2";
+ firmware = "firmware";
+ fdt = "fdt";
+ };
+ };
+};
diff --git a/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/visionfive2-u-boot-firmware.bb b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/visionfive2-u-boot-firmware.bb
new file mode 100644
index 00000000..b2303968
--- /dev/null
+++ b/meta-isar/recipes-bsp/visionfive2-u-boot-firmware/visionfive2-u-boot-firmware.bb
@@ -0,0 +1,36 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+inherit dpkg
+
+DESCRIPTION = "StarFive VisionFive 2 u-boot firmware"
+
+IMAGE_ITS_FILE = "visionfive2-uboot-fit-image.its"
+SRC_URI = " \
+ file://${IMAGE_ITS_FILE}.tmpl \
+ file://rules.tmpl \
+ file://visionfive2-u-boot-firmware.install"
+
+DEPENDS += "opensbi-starfive-visionfive2 linux-image-${KERNEL_NAME}"
+DEBIAN_BUILD_DEPENDS += "opensbi-starfive-visionfive2, u-boot-tools, device-tree-compiler, linux-image-${KERNEL_NAME}"
+
+TEMPLATE_FILES = "${IMAGE_ITS_FILE}.tmpl rules.tmpl"
+TEMPLATE_VARS = "IMAGE_ITS_FILE DTB_FILES"
+
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build(){
+ cp ${WORKDIR}/${IMAGE_ITS_FILE} ${S}/
+ cp ${WORKDIR}/visionfive2-u-boot-firmware.install ${S}/debian/
+ deb_debianize
+}
+
+do_deploy() {
+ dpkg --fsys-tarfile ${WORKDIR}/visionfive2-u-boot-firmware_${PV}*.deb | \
+ tar xOf - "./usr/share/visionfive2-u-boot-firmware/visionfive2_fw_payload.img" \
+ > "${DEPLOY_DIR_IMAGE}/visionfive2_fw_payload.img"
+}
+
+addtask deploy after do_dpkg_build before do_build
+do_deploy[dirs] = "${DEPLOY_DIR_IMAGE}"
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 7/7] starfive-visionfive2: add machine
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
` (5 preceding siblings ...)
2023-02-11 9:21 ` [PATCH v2 6/7] starfive-visionfive2: create u-boot-spl FIT image Felix Moessbauer
@ 2023-02-11 9:21 ` Felix Moessbauer
2023-03-14 15:31 ` [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Schaffner, Tobias
7 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-02-11 9:21 UTC (permalink / raw)
To: isar-users
Cc: jan.kiszka, daniel.bovensiepen, florian.bezdeka, jay.zhou,
Felix Moessbauer
This patch adds the RISCV64 based StarFive VisionFive 2 machine.
The target still needs a custom kernel and also only works from debian
bookworm on.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
meta-isar/conf/local.conf.sample | 1 +
.../conf/machine/starfive-visionfive2.conf | 29 +++++++++++++++++++
.../starfive-visionfive2-sid-ports.conf | 7 +++++
.../canned-wks/starfive-visionfive2.wks.in | 23 +++++++++++++++
4 files changed, 60 insertions(+)
create mode 100644 meta-isar/conf/machine/starfive-visionfive2.conf
create mode 100644 meta-isar/conf/multiconfig/starfive-visionfive2-sid-ports.conf
create mode 100644 meta-isar/scripts/lib/wic/canned-wks/starfive-visionfive2.wks.in
diff --git a/meta-isar/conf/local.conf.sample b/meta-isar/conf/local.conf.sample
index 7e0184e4..47f473a1 100644
--- a/meta-isar/conf/local.conf.sample
+++ b/meta-isar/conf/local.conf.sample
@@ -77,6 +77,7 @@ BBMULTICONFIG = " \
rpi-arm-v7l-bullseye \
rpi-arm64-v8-bullseye \
sifive-fu540-sid-ports \
+ starfive-visionfive2-sid-ports \
qemuarm64-focal \
qemuamd64-focal \
"
diff --git a/meta-isar/conf/machine/starfive-visionfive2.conf b/meta-isar/conf/machine/starfive-visionfive2.conf
new file mode 100644
index 00000000..a07b064f
--- /dev/null
+++ b/meta-isar/conf/machine/starfive-visionfive2.conf
@@ -0,0 +1,29 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+DISTRO_ARCH = "riscv64"
+
+KERNEL_NAME ?= "starfive"
+
+PREFERRED_PROVIDER_u-boot-starfive-visionfive2 = "u-boot-starfive-visionfive2"
+
+IMAGE_FSTYPES ?= "wic"
+
+WKS_FILE ?= "starfive-visionfive2.wks.in"
+IMAGER_INSTALL += " \
+ jh7110-u-boot-spl-image \
+ visionfive2-u-boot-firmware \
+ ${SYSTEMD_BOOTLOADER_INSTALL}"
+IMAGER_BUILD_DEPS += " \
+ jh7110-u-boot-spl-image \
+ visionfive2-u-boot-firmware"
+
+IMAGE_INSTALL += "sshd-regen-keys"
+IMAGE_INSTALL += "expand-on-first-boot"
+
+# DTB file for OpenSBI
+DTB_UBOOT_JH7110_VF2 = "starfive_visionfive2.dtb"
+# DTB file for booting
+DTB_FILES = "starfive/jh7110-visionfive-v2.dtb"
diff --git a/meta-isar/conf/multiconfig/starfive-visionfive2-sid-ports.conf b/meta-isar/conf/multiconfig/starfive-visionfive2-sid-ports.conf
new file mode 100644
index 00000000..98c9534a
--- /dev/null
+++ b/meta-isar/conf/multiconfig/starfive-visionfive2-sid-ports.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+MACHINE = "starfive-visionfive2"
+DISTRO = "debian-sid-ports"
diff --git a/meta-isar/scripts/lib/wic/canned-wks/starfive-visionfive2.wks.in b/meta-isar/scripts/lib/wic/canned-wks/starfive-visionfive2.wks.in
new file mode 100644
index 00000000..0f3d76a9
--- /dev/null
+++ b/meta-isar/scripts/lib/wic/canned-wks/starfive-visionfive2.wks.in
@@ -0,0 +1,23 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+# The partition layout is based on the VisionFive2 example image:
+# https://github.com/starfive-tech/VisionFive2/blob/JH7110_VisionFive2_devel/Makefile#L394
+# However, instead of booting via ubootenv + fit, we boot fit + efi
+#
+# When booting from the SD card, make sure that the DIP switches are set to SD card.
+# By that, the board reads the u-boot firmware from the SD instead of the internal flash.
+# This is required to boot efi with the correct device tree, which is included in the fit image.
+
+# SPL
+part --source rawcopy --sourceparams "file=/usr/share/jh7110-uboot-spl-image/u-boot-spl.bin.normal.out" --ondisk mmcblk1 --fixed-size 2M --offset 2M --part-type 2E54B353-1271-4842-806F-E436D6AF6985
+# U-Boot FIT
+part --source rawcopy --sourceparams "file=/usr/share/visionfive2-u-boot-firmware/visionfive2_fw_payload.img" --ondisk mmcblk1 --fixed-size 4M --offset 4M --part-type 5B193300-FC78-40CD-8002-E86C45580B47
+# EFI
+part /boot --source bootimg-efi-isar --sourceparams "loader=systemd-boot" --use-uuid --label efi --part-type EF00 --align 1024
+# rootfs
+part / --source rootfs --use-uuid --fstype ext4 --mkfs-extraopts "-T default" --label image --active --align 1024 --exclude-path=boot/
+
+bootloader --ptable gpt --timeout=0 --append "console=tty0 console=ttyS0,115200 earlycon rootwait"
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board
2023-02-11 9:21 [PATCH v2 0/7] Add BSP for StarFiveTech VisionFive2 Risc-V board Felix Moessbauer
` (6 preceding siblings ...)
2023-02-11 9:21 ` [PATCH v2 7/7] starfive-visionfive2: add machine Felix Moessbauer
@ 2023-03-14 15:31 ` Schaffner, Tobias
7 siblings, 0 replies; 12+ messages in thread
From: Schaffner, Tobias @ 2023-03-14 15:31 UTC (permalink / raw)
To: MOESSBAUER, FELIX JONATHAN, isar-users
Cc: Kiszka, Jan, daniel.bovensiepen, Bezdeka, Florian, jay.zhou
On 11.02.23 10:21, Felix Moessbauer wrote:
> Changes since v1:
>
> - rebased onto next (including bitbake 2.0 migration)
> - exclude opensbi memory range in u-boot DT
> - use upstream OpenSBI version (instead of StarFive version)
>
> This series adds a new machine "starfive-visionfive2" which is a
> Risc-V board based on the JH7110 SoC. The BSP is modeled based on the
> buildroot SDK [1], but without any proprietary imaging components.
>
> Further, we implement the fit + efi boot toolchain, instead of the
> proposed ubootenv + fit version. This also requires that we embed the
> board's linux device tree into the fit, as memory and reserved-memory
> nodes are resolved via the efi API (implemented by u-boot) instead of
> resolving them via the DT in Linux.
>
> As the JH7110 SoC has no usable upstream support yet, we directly
> build the 5.15 based kernel from the SDK, instead of porting patches
> on top of the standard Linux. Distro kernels are also not supported.
>
> Note: This series requires the following patch, which is NOT included:
> "fix cyclic dep on crossbuild-essential-riscv64"
>
> Best regards,
> Felix Moessbauer
> Siemens AG
I tested this series today. The isar-image-base target build and booted
just fine.
Best,
Tobias
> Felix Moessbauer (7):
> u-boot: inject debian multi-arch config
> starfive-visionfive2: package u-boot
> starfive-visionfive2: package opensbi firmware
> starfive-visionfive2: add BSP kernel
> starfive-visionfive2: create u-boot-spl firmware
> starfive-visionfive2: create u-boot-spl FIT image
> starfive-visionfive2: add machine
>
> meta-isar/conf/local.conf.sample | 1 +
> .../conf/machine/starfive-visionfive2.conf | 29 ++++++
> .../starfive-visionfive2-sid-ports.conf | 7 ++
> .../jh7110-u-boot-spl-image/files/install | 1 +
> .../jh7110-u-boot-spl-image/files/rules | 13 +++
> .../jh7110-u-boot-spl-image_0.1.bb | 30 +++++++
> .../jh7110-u-boot-spl-tool_0.1.bb | 23 +++++
> .../files/starfive-visionfive2-rules.tmpl | 17 ++++
> ...ensbi-starfive-visionfive2_1.2+20230107.bb | 31 +++++++
> ...x-offset-of-env-data-block-on-jh7110.patch | 30 +++++++
> ...iscv-Fix-build-against-binutils-2.38.patch | 55 ++++++++++++
> ...-opensbi-memory-range-in-device-tree.patch | 40 +++++++++
> ...upport-building-double-float-modules.patch | 89 +++++++++++++++++++
> ...five-visionfive2_2022.01-rc4+VF2-v2.8.0.bb | 38 ++++++++
> .../files/rules.tmpl | 12 +++
> .../files/visionfive2-u-boot-firmware.install | 1 +
> .../visionfive2-uboot-fit-image.its.tmpl | 41 +++++++++
> .../visionfive2-u-boot-firmware.bb | 36 ++++++++
> ...or-unrecognized-opcode-csrr-a5-0xc01.patch | 26 ++++++
> .../linux/files/starfive2_extra.cfg | 3 +
> .../linux/linux-starfive_5.15-visionfive2.bb | 18 ++++
> .../canned-wks/starfive-visionfive2.wks.in | 23 +++++
> .../u-boot/files/debian/rules.tmpl | 9 ++
> 23 files changed, 573 insertions(+)
> create mode 100644 meta-isar/conf/machine/starfive-visionfive2.conf
> create mode 100644 meta-isar/conf/multiconfig/starfive-visionfive2-sid-ports.conf
> create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/install
> create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-image/files/rules
> create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-image/jh7110-u-boot-spl-image_0.1.bb
> create mode 100644 meta-isar/recipes-bsp/jh7110-u-boot-spl-tool/jh7110-u-boot-spl-tool_0.1.bb
> create mode 100644 meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl
> create mode 100644 meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb
> create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-fix-offset-of-env-data-block-on-jh7110.patch
> create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0001-riscv-Fix-build-against-binutils-2.38.patch
> create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-exclude-opensbi-memory-range-in-device-tree.patch
> create mode 100644 meta-isar/recipes-bsp/u-boot/files/starfive-visionfive2/0002-riscv-support-building-double-float-modules.patch
> create mode 100644 meta-isar/recipes-bsp/u-boot/u-boot-starfive-visionfive2_2022.01-rc4+VF2-v2.8.0.bb
> create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/rules.tmpl
> create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-u-boot-firmware.install
> create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/files/visionfive2-uboot-fit-image.its.tmpl
> create mode 100644 meta-isar/recipes-bsp/visionfive2-u-boot-firmware/visionfive2-u-boot-firmware.bb
> create mode 100644 meta-isar/recipes-kernel/linux/files/fix-Error-unrecognized-opcode-csrr-a5-0xc01.patch
> create mode 100644 meta-isar/recipes-kernel/linux/files/starfive2_extra.cfg
> create mode 100644 meta-isar/recipes-kernel/linux/linux-starfive_5.15-visionfive2.bb
> create mode 100644 meta-isar/scripts/lib/wic/canned-wks/starfive-visionfive2.wks.in
>
^ permalink raw reply [flat|nested] 12+ messages in thread