Re: [PATCH] CI: Protect Debian Ports targets by KFAIL

[Jan Kiszka <jan.kiszka@siemens.com>]

On 31.01.22 10:45, Anton Mikanovich wrote:
> Upstream was broken few days ago, so we need to apply hotfix ASAP before 
> release.
> Will also apply this today if no objections.
> 

sid can only be KFAIL. If you want a reliable test for the risc-v 
targets, you would need to pin to a archived repo revision. But then the 
downloading from snapshot.debian.org will not work reliably...

Jan

> 31.01.2022 12:43, Anton Mikanovich wrote:
>> Debian Ports provides unofficial architectures support which not always
>> stable enough.
>> Currently few sifive-fu540-sid-ports recipes fail with:
>>
>> opensbi-0.9/lib/sbi/sbi_tlb.c: Assembler messages:
>> opensbi-0.9/lib/sbi/sbi_tlb.c:175: Error: unrecognized opcode `fence.i'
>> ...
>> ../arch/riscv/include/asm/timex.h: Assembler messages:
>> ../arch/riscv/include/asm/timex.h:15: Error: unrecognized opcode `csrr 
>> a5,0xc01'
>> ../arch/riscv/include/asm/timex.h:15: Error: unrecognized opcode `csrr 
>> a1,0xc01'
>> ../arch/riscv/include/asm/timex.h:15: Error: unrecognized opcode `csrr 
>> a1,0xc01'
>> ../arch/riscv/include/asm/timex.h:15: Error: unrecognized opcode `csrr 
>> t4,0xc01'
>> ../arch/riscv/include/asm/timex.h:15: Error: unrecognized opcode `csrr 
>> a5,0xc01'
>> ../arch/riscv/include/asm/timex.h:15: Error: unrecognized opcode `csrr 
>> a5,0xc01'
>> ../arch/riscv/include/asm/timex.h:15: Error: unrecognized opcode `csrr 
>> a2,0xc01'
>>
>> To not block other targets cover both sid-ports targets with KFAIL.
>>
>> Signed-off-by: Anton Mikanovich <amikan@ilbers.de>
>> ---
>>   testsuite/build_test/build_test.py | 13 +++++++++++--
>>   1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/testsuite/build_test/build_test.py 
>> b/testsuite/build_test/build_test.py
>> index 683aa55d..16f6d0a3 100644
>> --- a/testsuite/build_test/build_test.py
>> +++ b/testsuite/build_test/build_test.py
>> @@ -124,8 +124,6 @@ class NoCrossTest(CIBaseTest):
>>               'mc:qemuamd64-bullseye:isar-initramfs',
>>               'mc:qemumipsel-buster:isar-image-base',
>>               'mc:qemumipsel-bullseye:isar-image-base',
>> -            'mc:qemuriscv64-sid-ports:isar-image-base',
>> -            'mc:sifive-fu540-sid-ports:isar-image-base',
>>               'mc:imx6-sabrelite-bullseye:isar-image-ubi',
>>               'mc:phyboard-mira-bullseye:isar-image-ubi',
>>               'mc:rpi-arm-bullseye:isar-image-base',
>> @@ -160,6 +158,17 @@ class NoCrossTest(CIBaseTest):
>>           except:
>>               self.cancel('KFAIL')
>> +    def test_nocross_sidports(self):
>> +        targets = [
>> +            'mc:qemuriscv64-sid-ports:isar-image-base',
>> +            'mc:sifive-fu540-sid-ports:isar-image-base'
>> +                  ]
>> +
>> +        try:
>> +            self.perform_build_test(targets, 0, None)
>> +        except:
>> +            self.cancel('KFAIL')
>> +
>>   class RebuildTest(CIBaseTest):
>>       """
> 

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